Rob A. Rutenbar

According to our database1, Rob A. Rutenbar authored at least 155 papers between 1981 and 2020.

Collaborative distances:

Awards

ACM Fellow

ACM Fellow 2008, "For contributions to computer-aided design tools for mixed-signal integrated circuits.".

IEEE Fellow

IEEE Fellow 1998, "For contributions to computer aided design tools for automatic synthesis and layout of analog and mixed-signal integrated circuits.".

Timeline

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Bibliography

2020
A 3mm<sup>2</sup> Programmable Bayesian Inference Accelerator for Unsupervised Machine Perception using Parallel Gibbs Sampling in 16nm.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A Scalable Bayesian Inference Accelerator for Unsupervised Learning.
Proceedings of the IEEE Hot Chips 32 Symposium, 2020

Studying the Potential of Automatic Optimizations in the Intel FPGA SDK for OpenCL.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

Hardware Architecture of a Number Theoretic Transform for a Bootstrappable RNS-based Homomorphic Encryption Scheme.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2019
FPGA-based Accelerators of Fully Pipelined Modular Multipliers for Homomorphic Encryption.
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019

An Area-Efficient Iterative Single-Precision Floating-Point Multiplier Architecture for FPGA.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Accelerating Bayesian Inference on Structured Graphs Using Parallel Gibbs Sampling.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

A Pixel-Parallel Virtual-Image Architecture for High Performance and Power Efficient Graph Cuts Inference.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

FlexGibbs: Reconfigurable Parallel Gibbs Sampling Accelerator for Structured Graphs.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

A Virtual Image Accelerator for Graph Cuts Inference on FPGA.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018
Real-Time and Low-Power Streaming Source Separation Using Markov Random Field.
ACM J. Emerg. Technol. Comput. Syst., 2018

Realizing the potential of data science.
Commun. ACM, 2018

Accelerator Design with Effective Resource Utilization for Binary Convolutional Neural Networks on an FPGA.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017
A case study of machine learning hardware: Real-time source separation using Markov Random Fields via sampling-based inference.
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017

Toward a pixel-parallel architecture for graph cuts inference on FPGA.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016
Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Video-Rate Stereo Matching Using Markov Random Field TRW-S Inference on a Hybrid CPU+FPGA Computing Platform.
IEEE Trans. Circuits Syst. Video Technol., 2016

Keynote address Wednesday: Hardware inference accelerators for machine learning.
Proceedings of the 2016 IEEE International Test Conference, 2016

Analysis of error resiliency of belief propagation in computer vision.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

Configurable and scalable belief propagation accelerator for computer vision.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015
Analog Circuit and Layout Synthesis Revisited.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

Fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inference.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

2014
DAC at 50: The Second 25 Years.
IEEE Des. Test, 2014

A robust message passing based stereo matching kernel via system-level error resiliency.
Proceedings of the IEEE International Conference on Acoustics, 2014

The First EDA MOOC: Teaching Design Automation to Planet Earth.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Efficiently Enforcing Diversity in Multi-Output Structured Prediction.
Proceedings of the Seventeenth International Conference on Artificial Intelligence and Statistics, 2014

2013
Efficient Spatial Pattern Analysis for Variation Decomposition Via Robust Sparse Regression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Error resilient MRF message passing architecture for stereo matching.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

FPGA acceleration of Markov Random Field TRW-S inference for stereo matching.
Proceedings of the 11th ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2013

EMERALD: Characterization of emerging applications and algorithms for low-power devices.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

Automatic clustering of wafer spatial signatures.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Stereophonic spectrogram segmentation using Markov random fields.
Proceedings of the IEEE International Workshop on Machine Learning for Signal Processing, 2012

Spatial variation decomposition via sparse regression.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

Hardware implementation of MRF map inference on an FPGA platform.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

A High-Rate, Low-Power, ASIC Speech Decoder Using Finite State Transducers.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

2011
Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Toward efficient spatial variation decomposition via sparse regression.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010
Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Why Quasi-Monte Carlo is Better Than Monte Carlo or Latin Hypercube Sampling for Statistical Circuit Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Analog layout synthesis: what's missing?
Proceedings of the 2010 International Symposium on Physical Design, 2010

Multi-Wafer Virtual Probe: Minimum-cost variation characterization by exploring wafer-to-wafer correlation.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Bayesian virtual probe: minimizing variation characterization cost for nanoscale IC technologies via Bayesian inference.
Proceedings of the 47th Design Automation Conference, 2010

2009
Novel Algorithms for Fast Statistical Analysis of Scaled Circuits
Lecture Notes in Electrical Engineering 46, Springer, ISBN: 978-90-481-3099-3, 2009

Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Profiling large-vocabulary continuous speech recognition on embedded devices: a hardware resource sensitivity analysis.
Proceedings of the INTERSPEECH 2009, 2009

Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

A multi-fpga 10x-real-time high-speed search engine for a 5000-word vocabulary speech recognizer.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Oil fields, hedge funds, and drugs.
Proceedings of the 46th Design Automation Conference, 2009

2008
Probabilistic Interval-Valued Computation: Toward a Practical Surrogate for Statistics Inside CAD Tools.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS.
Proc. IEEE, 2008

Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

A low-power hardware search architecture for speech recognition.
Proceedings of the INTERSPEECH 2008, 2008

Practical, fast Monte Carlo statistical static timing analysis: why and how.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Exploiting Correlation Kernels for Efficient Handling of Intra-Die Spatial Correlation, with Application to Statistical Timing.
Proceedings of the Design, Automation and Test in Europe, 2008

Verifying really complex systems: on earth and beyond.
Proceedings of the 45th Design Automation Conference, 2008

2007
Interval-Valued Reduced-Order Statistical Interconnect Modeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs.
Proc. IEEE, 2007

Collaborative VLSI-CAD Instruction in the Digital Sandbox.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit Analysis.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Mixed-size placement with fixed macrocells using grid-warping.
Proceedings of the 2007 International Symposium on Physical Design, 2007

Generating small, accurate acoustic models with a modified Bayesian information criterion.
Proceedings of the INTERSPEECH 2007, 2007

A 1000-word vocabulary, speaker-independent, continuous live-mode speech recognizer implemented in a single FPGA.
Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007

Statistical blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its application.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting.
Proceedings of the 44th Design Automation Conference, 2007

Next-Generation Design and EDA Challenges: Small Physics, Big Systems, and Tall Tool-Chains.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Fast Interval-Valued Statistical Modeling of Interconnect and Effective Capacitance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Time Domain Verification of Oscillator Circuit Properties.
Electron. Notes Theor. Comput. Sci., 2006

Moving speech recognition from software to silicon: the in silico vox project.
Proceedings of the INTERSPEECH 2006, 2006

Faster, parametric trajectory-based macromodels via localized linear reductions.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Design automation for analog: the next generation of tool challenges.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Verifying analog oscillator circuits using forward/backward abstraction refinement.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration.
Proceedings of the 43rd Design Automation Conference, 2006

On-the-Fly Fidelity Assessment for Trajectory-Based Circuit Macromodels.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
Early research experience with OpenAccess gear: an open source development environment for physical design.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Fast interval-valued statistical interconnect modeling and reduction.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Interval-valued statistical modeling of oxide chemical-mechanical polishing.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters.
Proceedings of the 2005 Design, 2005

Timing-driven placement by grid-warping.
Proceedings of the 42nd Design Automation Conference, 2005

Scalable trajectory methods for on-demand analog macromodel extraction.
Proceedings of the 42nd Design Automation Conference, 2005

2004
A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints.
IEEE Trans. Computers, 2004

Static statistical timing analysis for latch-based pipeline designs.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Towards formal verification of analog designs.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits.
Proceedings of the 41th Design Automation Conference, 2004

Large-scale placement by grid-warping.
Proceedings of the 41th Design Automation Conference, 2004

Will Moore's Law rule in the land of analog?
Proceedings of the 41th Design Automation Conference, 2004

2003
sub-SAT: a formulation for relaxed Boolean satisfiability with applications in routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Floating-point error analysis based on affine arithmetic.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

Mixed signals on mixed-signal: the right next technology.
Proceedings of the 40th Design Automation Conference, 2003

Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling.
Proceedings of the 40th Design Automation Conference, 2003

2002
A new FPGA detailed routing approach via search-based Booleansatisfiability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Lightweight Floating-Point Arithmetic: Case Study of Inverse Discrete Cosine Transform.
EURASIP J. Adv. Signal Process., 2002

Floating-point bit-width optimization for low-power signal processing applications.
Proceedings of the IEEE International Conference on Acoustics, 2002

Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search.
Proceedings of the Field-Programmable Logic and Applications, 2002

Remembrance of circuits past: macromodeling by data mining in large analog design spaces.
Proceedings of the 39th Design Automation Conference, 2002

2001
Wire packing - a strong formulation of crosstalk-aware chip-leveltrack/layer assignment with an efficient integer programming solution.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Low-power technology mapping for mixed-swing logic.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Automatic Hierarchical Design: Fantasy or Reality? (Panel).
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Embedded Tutorial: CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Analog Circuits.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Direct Transistor-Level Layout for Digital Blocks.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Synthesis for Industrial-Scale Analog Intellectual Property.
Proceedings of the 3rd NASA / DoD Workshop on Evolvable Hardware (EH 2001), 2001

A boolean satisfiability-based incremental rerouting approach with application to FPGAs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Panel: (When) Will FPGAs Kill ASICs?
Proceedings of the 38th Design Automation Conference, 2001

2000
Reducing power by optimizing the necessary precision/range of floating-point arithmetic.
IEEE Trans. Very Large Scale Integr. Syst., 2000

Anaconda: simulation-based synthesis of analog circuits viastochastic pattern search.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Efficient handling of operating range and manufacturing linevariations in analog cell synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Layout tools for analog ICs and mixed-signal SoCs: a survey.
Proceedings of the 2000 International Symposium on Physical Design, 2000

Wire packing: a strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution.
Proceedings of the 2000 International Symposium on Physical Design, 2000

Life at the end of CMOS scaling (and beyond) (panel session) (abstract only).
Proceedings of the 37th Conference on Design Automation, 2000

A case study of synthesis for industrial-scale analog IP: redesign of the equalizer/filter frontend for an ADSL CODEC.
Proceedings of the 37th Conference on Design Automation, 2000

Survival strategies for mixed-signal systems-on-chip (panel session).
Proceedings of the 37th Conference on Design Automation, 2000

Case studies: Chip design on the bleeding edge (panel session abstract).
Proceedings of the 37th Conference on Design Automation, 2000

1999
Device-level early floorplanning algorithms for RF circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Satisfiability-Based Detailed FPGA Routing.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Inverse polarity techniques for high-speed/low-power multipliers.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs vis Search-Based Boolean SAT.
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

MAELSTROM: Efficient Simulation-Based Synthesis for Custom Analog Cells.
Proceedings of the 36th Conference on Design Automation, 1999

1998
FPGA routing and routability estimation via Boolean satisfiability.
IEEE Trans. Very Large Scale Integr. Syst., 1998

Performance-driven simultaneous placement and routing for FPGA's.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

1997
A hierarchical decomposition methodology for multistage clock circuits.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996
Synthesis of high-performance analog circuits in ASTRX/OBLX.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend Strategies.
Proceedings of the 33st Conference on Design Automation, 1996

An <i>O(n)</i> Algorithm for Transistor Stacking with Performance Constraints.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Integer programming based topology selection of cell-level analog circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Testability-oriented channel routing.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Performance-driven simultaneous place and route for island-style FPGAs.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1994
Synthesis of manufacturable analog circuits.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

ASTRX/OBLX: Tools for Rapid Synthesis of High-Performance Analog Circuits.
Proceedings of the 31st Conference on Design Automation, 1994

Performance-Driven Simultaneous Place and Route for Row-Based FPGAs.
Proceedings of the 31st Conference on Design Automation, 1994

1993
Latchup-aware placement and parasitic-bounded routing of custom analog cells.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992
Knowledge Representation and Reasoning in a Software Synthesis Architecture.
IEEE Trans. Software Eng., 1992

System-level routing of mixed-signal ASICs in WREN.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

A Mixed-Integer Nonlinear Programming Approach to Analog Circuit Synthesis.
Proceedings of the 29th Design Automation Conference, 1992

1991
On the feasibility of synthesizing CAD software from specifications: generating maze router tools in ELF.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Massively parallel switch-level simulation: a feasibility study.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

A Parallel Steiner Heuristic for Wirelength Estimation of Large Net Populations.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Techniques for Simultaneous Placement and Routing of Custom Analog Cells in KOAN/ANAGRAM II.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

1990
Design and Performance Evaluation of New Massively Parallel VLSI Mask Verification Algorithms in JIGSAW.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989
OASYS: a framework for analog circuit synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Logic Simulation on Massively Parallel Architectures.
Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989

Zen and the Art of Analog Design Automation.
Proceedings of the Information Processing 89, Proceedings of the IFIP 11th World Computer Congress, San Francisco, USA, August 28, 1989

ELF: A Tool for Automatic Synthesis of Custom Physical CAD Software.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988
Systolic routing hardware: performance evaluation and optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

Analog circuit synthesis for performance in OASYS.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Automatic layout of custom analog cells in ANAGRAM.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Mask Verification on the Connection Machine.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987
Placement by Simulated Annealing on a Multiprocessor.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

A Scanline Data Structure Processor for VLSI Geometry Checking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

A Prototype Framework for Knowledge-Based Analog Circuit Synthesis.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1986
Multiprocessor-based placement by simulated annealing.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1985
Future directions for DA machine research (panel session).
Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

1984
A Class of Cellular Architectures to Support Physical Design Automation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984

1982
Cellular image processing techniques for VLSI circuit layout validation and routing.
Proceedings of the 19th Design Automation Conference, 1982

1981
Case study of a VLSI design project: A simple inner product machine.
Proceedings of the 5th IEEE Symposium on Computer Arithmetic, 1981


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