Rajiv A. Ravindran

According to our database, Rajiv A. Ravindran authored at least 12 papers between 2001 and 2007.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2007

Hardware/software techniques for memory power optimizations in embedded processors.

Rajiv A. Ravindran

PhD thesis, 2007

Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures.

Michael L. Chu, Rajiv A. Ravindran, Scott A. Mahlke

Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

Compiler-managed partitioned data caches for low power.

Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlke

Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, 2007

2005

Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor.

Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown

IEEE Trans. Computers, 2005

Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache.

Rajiv A. Ravindran, Pracheeti D. Nagarkar, Ganesh S. Dasika, Eric D. Marsman, Robert M. Senger, Scott A. Mahlke, Richard B. Brown

Proceedings of the 3nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2005), 2005

2004

Cost-Sensitive Partitioning in an Architecture Synthesis System for Multicluster Processors.

Michael L. Chu, Kevin Fan, Rajiv A. Ravindran, Scott A. Mahlke

IEEE Micro, 2004

FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths.

Manjunath Kudlur, Kevin Fan, Michael L. Chu, Rajiv A. Ravindran, Nathan Clark, Scott A. Mahlke

Proceedings of the 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 2004

2003

Increasing the number of effective registers in a low-power processor using a windowed register file.

Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown

Proceedings of the International Conference on Compilers, 2003

Systematic Register Bypass Customization for Application-Specific Processors.

Kevin Fan, Nathan Clark, Michael L. Chu, K. V. Manjunath, Rajiv A. Ravindran, Mikhail Smelyanskiy, Scott A. Mahlke

Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

2001

Bitwidth cognizant architecture synthesis of custom hardwareaccelerators.

Scott A. Mahlke, Rajiv A. Ravindran, Michael S. Schlansker, Robert Schreiber, Timothy Sherwood

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Retargetable Program Profiling Using High Level Processor Models.

Rajiv A. Ravindran, Rajat Moona

Proceedings of the High Performance Computing - HiPC 2001, 8th International Conference, 2001

Retargetable Cache Simulation Using High Level Processor Models.

Rajiv A. Ravindran, Rajat Moona

Proceedings of the 6th Australasian Computer Systems Architecture Conference (ACSAC 2001), 2001