Robert M. Senger

Orcid: 0000-0002-0360-7014

According to our database1, Robert M. Senger authored at least 20 papers between 2003 and 2024.

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Bibliography

2024

2023
Data Movement Accelerator Engines on a Prototype Power10 Processor.
IEEE Micro, 2023

2014
Soft error resiliency characterization and improvement on IBM BlueGene/Q processor using accelerated proton irradiation.
Proceedings of the 2014 International Test Conference, 2014

Soft Error Resiliency Characterization on IBM BlueGene/Q Processor.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Single-cycle, pulse-shaped critical path monitor in the POWER7+ microprocessor.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

2012
The IBM Blue Gene/Q Interconnection Fabric.
IEEE Micro, 2012

Looking under the hood of the IBM blue gene/Q network.
Proceedings of the SC Conference on High Performance Computing Networking, 2012

2011
The IBM Blue Gene/Q interconnection network and message unit.
Proceedings of the Conference on High Performance Computing Networking, 2011

2007
A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
A dual-V<sub>DD</sub> boosted pulsed bus technique for low power and low leakage operation.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Low-latency, HDL-synthesizable dynamic clock frequency controller with self-referenced hybrid clocking.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

DSP architecture for cochlear implants.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 16-bit, low-power microsystem with monolithic MEMS-<i>LC</i> clocking.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor.
IEEE Trans. Computers, 2005

A 16-bit low-power microcontroller with monolithic MEMS-LC clocking.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache.
Proceedings of the 3nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2005), 2005

2003
Microsystem and SoC Design with UMIPS.
Proceedings of the IFIP VLSI-SoC 2003, 2003

A Top-Down Microsystems Design Methodology and Associated Challenges .
Proceedings of the 2003 Design, 2003

A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference.
Proceedings of the 40th Design Automation Conference, 2003

Increasing the number of effective registers in a low-power processor using a windowed register file.
Proceedings of the International Conference on Compilers, 2003


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