Ram Kelkar

According to our database, Ram Kelkar authored at least 4 papers between 1995 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology.

John F. Bulzacchelli, Christian Menolfi, Troy J. Beukema, Daniel W. Storaska, Juergen Hertle, David Hanson, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, W. R. Kelly, L. R. Chieco, Glenn Ritter, J. A. Sorice, Jon Garlett, Robert Callan, Matthias Braendli, Peter Buchmann, Marcel A. Kossel, Thomas Toifl, Daniel J. Friedman

IEEE J. Solid State Circuits, 2012

A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology.

John F. Bulzacchelli, Troy J. Beukema, Daniel W. Storaska, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Christian Menolfi, David Hanson, Juergen Hertle, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, William Kelly, Glenn Ritter, Jon Garlett, Robert Callan, Thomas Toifl, Daniel J. Friedman

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2005

A Low Jitter Programmable Frequency Synthesizer for 4.25Gbps Serial Link Applications.

Ram Kelkar, Dave Flye, Anjali Malladi, Joseph Natonio, Chri Scoville, Ken Short, Pradeep Thiagarajan

Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

1995

Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and ∓50 ps jitter.

Ilya I. Novof, John Austin, Ram Kelkar, Don Strayer, Steve Wyatt

IEEE J. Solid State Circuits, November, 1995