John F. Bulzacchelli
Orcid: 0000-0002-8803-9553
According to our database1,
John F. Bulzacchelli
authored at least 44 papers
between 2002 and 2023.
Collaborative distances:
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Bibliography
2023
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links.
IEEE J. Solid State Circuits, 2023
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A Cryo-CMOS Low-Power Semi-Autonomous Transmon Qubit State Controller in 14-nm FinFET Technology.
IEEE J. Solid State Circuits, 2022
An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A Cryo-CMOS Low-Power Semi-Autonomous Qubit State Controller in 14nm FinFET Technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2020
Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14-nm SOI CMOS.
IEEE J. Solid State Circuits, 2020
Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS".
IEEE J. Solid State Circuits, 2020
IEEE J. Solid State Circuits, 2020
2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14nm SOI CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
IEEE J. Solid State Circuits, 2018
2016
A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration.
IEEE J. Solid State Circuits, 2016
2015
IEEE J. Solid State Circuits, 2015
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.
IEEE J. Solid State Circuits, 2015
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2015
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2014
5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8<sup>TM</sup> microprocessor.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2012
An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects.
IEEE J. Solid State Circuits, 2012
IEEE J. Solid State Circuits, 2012
Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage.
IEEE J. Solid State Circuits, 2012
A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS.
IEEE J. Solid State Circuits, 2012
Proceedings of the 2012 IEEE International Test Conference, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2009
IEEE J. Solid State Circuits, 2009
A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2009
Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2007
IEEE J. Solid State Circuits, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
IEEE J. Solid State Circuits, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2003
A superconducting bandpass delta-sigma modulator for direct analog-to-digital conversion of microwave radio.
PhD thesis, 2003
2002
Superconducting bandpass ΔΣ modulator with 2.23-GHz center frequency and 42.6-GHz sampling rate.
IEEE J. Solid State Circuits, 2002