Ramy N. Tadros

According to our database, Ramy N. Tadros authored at least 11 papers between 2014 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

The 2010 Census Confidentiality Protections Failed, Here's How and Why.

John M. Abowd, Tamara Adams, Robert Ashmead, David Darais, Sourya Dey, Simson L. Garfinkel, Nathan Goldschlag, Daniel Kifer, Philip Leclerc, Ethan Lew, Scott Moore, Rolando A. Rodríguez, Ramy N. Tadros, Lars Vilhuber

CoRR, 2023

2020

A Theoretical Foundation for Timing Synchronous Systems Using Asynchronous Structures.

Ramy N. Tadros, Peter A. Beerel

ACM Trans. Design Autom. Electr. Syst., 2020

2018

A Robust and Self-Adaptive Clocking Technique for RSFQ Circuits - The Architecture.

Ramy N. Tadros, Peter A. Beerel

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2016

A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI.

Ramy N. Tadros, Weizhe Hua, Matheus T. Moreira, Ney Laert Vilar Calazans, Peter A. Beerel

IEEE Trans. Circuits Syst. II Express Briefs, 2016

A Fine-Grain, Uniform, Energy-Efficient Delay Element for 2-Phase Bundled-Data Circuits.

Ajay Singhvi, Matheus T. Moreira, Ramy N. Tadros, Ney Laert Vilar Calazans, Peter A. Beerel

ACM J. Emerg. Technol. Comput. Syst., 2016

Low Area, Low Power, Robust, Highly Sensitive Error Detecting Latch for Resilient Architectures.

Weizhe Hua, Ramy N. Tadros, Peter A. Beerel

Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications.

Ramy N. Tadros, Weizhe Hua, Matheus Gibiluka, Matheus T. Moreira, Ney Laert Vilar Calazans, Peter A. Beerel

Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016

2015

A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies.

Ajay Singhvi, Matheus T. Moreira, Ramy N. Tadros, Ney Laert Vilar Calazans, Peter A. Beerel

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A 24 Gbps SerDes transceiver for on-chip networks using a new half-data-rate self-timed 3-level signaling scheme.

Ramy N. Tadros, Ahmed H. Abdelrahman, Maged Ghoneima, Yehea Ismail

Proceedings of the 5th International Conference on Energy Aware Computing Systems & Applications, 2015

2014

A variation tolerant driving technique for all-digital self-timed 3-level signaling high-speed SerDes transceivers for on-chip networks.

Ramy N. Tadros, Abdelrahman H. Elsayed, Maged Ghoneima, Yehea I. Ismail

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Low-power all-digital manchester-encoding-based high-speed serdes transceiver for on-chip networks.

Abdelrahman H. Elsayed, Ramy N. Tadros, Maged Ghoneima, Yehea I. Ismail

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014