Ney Laert Vilar Calazans

Affiliations:
  • Pontifical Catholic University of Rio Grande do Sul, PUCRS, Brazil


According to our database1, Ney Laert Vilar Calazans authored at least 129 papers between 1994 and 2021.

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Bibliography

2021
Quasi Delay Insensitive FIFOs: Design Choices Exploration and Comparison.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Towards an Integrated Software Development Environment for Robotic Applications in MPSoCs with Support for Energy Estimations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Leveraging QDI Robustness to Simplify the Design of IoT Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A Frontend using Traditional EDA Tools for the Pulsar QDI Design Flow.
Proceedings of the 26th IEEE International Symposium on Asynchronous Circuits and Systems, 2020

2019
An IR-UWB pulse generator using PAM modulation with adaptive PSD in 130nm CMOS process.
Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019

Asynchronous Quasi-Random Number Generator: Taking Advantage of PVT Variations.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools.
Proceedings of the 25th IEEE International Symposium on Asynchronous Circuits and Systems, 2019

2018
NCL Synthesis With Conventional EDA Tools: Technology Mapping and Optimization.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2017
Sleep convention logic isochronic fork: an analysis.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

A comparison of asynchronous QDI templates using static logic.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Go functional model for a RISC-V asynchronous organisation - ARV.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

XGT4: An industrial grade, open source tester for multi-gigabit networks.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Hardening C-elements against metastability.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

2016
Testable MUTEX Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A processor for IoT applications: An assessment of design space and trade-offs.
Microprocess. Microsystems, 2016

A Fine-Grain, Uniform, Energy-Efficient Delay Element for 2-Phase Bundled-Data Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2016

A standard cell characterization flow for non-standard voltage supplies.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

Design and analysis of the HF-RISC processor targeting voltage scaling applications.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

The HF-RISC processor: Performance assessment.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

ASCEnD-FreePDK45: An open source standard cell library for asynchronous design.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications.
Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016

2015
Static Differential NCL Gates: Toward Low Power.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits.
Proceedings of the 28th International Conference on VLSI Design, 2015

SDDS-NCL Design: Analysis of Supply Voltage Scaling.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

A digitally controlled oscillator for fine-grained local clock generators in MPSoCs.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

BAT-Hermes: A transition-signaling bundled-data NoC router.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

TDTB error detecting latches: Timing violation sensitivity analysis and optimization.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

A path towards average-case silicon via asynchronous resilient bundled-data design.
Proceedings of the European Conference on Circuit Theory and Design, 2015

A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Design and Analysis of Testable Mutual Exclusion Elements.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

Blade - A Timing Violation Resilient Asynchronous Template.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

Performance Optimization and Analysis of Blade Designs under Delay Variability.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

2014
Beware the Dynamic C-Element.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Differentiated Communication Services for NoC-Based MPSoCs.
IEEE Trans. Computers, 2014

System-level impacts of persistent main memory using a search engine.
Microelectron. J., 2014

MoNoC: A monitored network on chip with path adaptation mechanism.
J. Syst. Archit., 2014

Spatially Distributed Dual-Spacer Null Convention Logic Design.
J. Low Power Electron., 2014

Advances on the state of the art in QDI design.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Automated Synthesis of Cell Libraries for Asynchronous Circuits.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

Schmitt trigger on output inverters of NCL gates for soft error hardening: Is it enough?
Proceedings of the 15th Latin American Test Workshop, 2014

Automatic layout synthesis with ASTRAN applied to asynchronous cells.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

A monitored NoC with runtime path adaptation.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A design flow for physical synthesis of digital cells with ASTRAN.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Hardening QDI circuits against transient faults using delay-insensitive maxterm synthesis.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014

A New CMOS Topology for Low-Voltage Null Convention Logic Gates Design.
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014

2013
H2A: A hardened asynchronous network on chip.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

Lasio 3D NoC vertical links serialization: Evaluation of latency and buffer occupancy.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

BaBaNoC: An asynchronous network-on-chip described in Balsa.
Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013

NCL+: Return-to-one Null Convention Logic.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Design of NCL gates with the ASCEnD flow.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Design of standard-cell libraries for asynchronous circuits with the ASCEnD flow.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Evaluating the scalability of test buses.
Proceedings of the 2013 International Symposium on System on Chip, 2013

Parity check for m-of-n delay insensitive codes.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

A flexible soft IP core for standard implementations of elliptic curve cryptography in hardware.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Voltage scaling on C-elements: A speed, power and energy efficiency analysis.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell Libraries.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Charge sharing aware NCL gates design.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2012
Power consumption reduction in MPSoCs through DFS.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

A spectrum of MPSoC models for design space exploration and its use.
Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012

A preliminary study on system-level impact of persistent main memory.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Impact of C-elements in asynchronous circuits.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Return-to-One DIMS logic on 4-phase m-of-n asynchronous circuits.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Electrical characterization of a C-Element with LiChEn.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

A generic FPGA emulation framework.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

An accurate Single Event Effect digital design flow for reliable system level design.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects.
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012

2011
CAFES: A framework for intrachip application modeling and communication architecture design.
J. Parallel Distributed Comput., 2011

A Robust Architectural Approach for Cryptographic Algorithms Using GALS Pipelines.
IEEE Des. Test Comput., 2011

A 65nm standard cell set and flow dedicated to automated asynchronous circuits design.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

A self-adaptable distributed DFS scheme for NoC-based MPSoCs.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Arbitration and routing impact on NoC design.
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

Adapting a C-element design flow for low power.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010
Dynamic Task Mapping for MPSoCs.
IEEE Des. Test Comput., 2010

Hermes-AA: A 65nm asynchronous NoC router with adaptive routing.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Implementation and evaluation of a congestion aware routing algorithm for networks-on-chip.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

A GALS pipeline DES architecture to increase robustness against DPA and DEMA attacks.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

Hermes-A - An Asynchronous NoC Router with Distributed Routing.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

2009
Floating Point Hardware for Embedded Processors in FPGAs: Design Space Exploration for Performance and Area.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

A 10 Gbps OTN Framer Implementation Targeting FPGA Devices.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Evaluation of static and dynamic task mapping algorithms in NoC-based MPSoCs.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

HeMPS - a Framework for NoC-based MPSoC Generation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Evaluation on FPGA of triple rail logic robustness against DPA and DEMA.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Comparison of network-on-chip mapping algorithms targeting low energy consumption.
IET Comput. Digit. Tech., 2008

Evaluating the robustness of secure triple track logic through prototyping.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

MOTIM: an industrial application using nocs.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

Integrating Abstract NoC Models within MPSoC Design.
Proceedings of the 19th IEEE/IFIP International Symposium on Rapid System Prototyping: RSP 2009, 2008

Triple Rail Logic Robustness against DPA.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

NoC Power Estimation at the RTL Abstraction Level.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

2007
QoS in Networks-on-Chip - Beyond Priority and Circuit Switching Techniques.
Proceedings of the VLSI-SoC: Advanced Topics on Systems on a Chip, 2007

Rate-based scheduling policy for QoS flows in networks on chip.
Proceedings of the IFIP VLSI-SoC 2007, 2007

Buffer sizing for QoS flows in wormhole packet switching NoCs.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

Router architecture for high-performance NoCs.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

SPP-NIDS - A Sea of Processors Platform for Network Intrusion Detection Systems.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable Systems.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic Workload.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

MOTIM - A Scalable Architecture for Ethernet Switches.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Evaluation of Algorithms for Low Energy Mapping onto NoCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

SCAFFI: An intrachip FPGA asynchronous interface based on hard macros.
Proceedings of the 25th International Conference on Computer Design, 2007

2006
Application driven traffic modeling for NoCs.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Infrastructure for dynamic reconfigurable systems: choices and trade-offs.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Evaluation of current QoS Mechanisms in Networks on Chip.
Proceedings of the International Symposium on System-on-Chip, 2006

Reconfigurable Systems Enabled by a Network-on-Chip.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005
Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

Traffic generation and performance evaluation for mesh-based NoCs.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Virtual channels in networks on chip: implementation and evaluation on hermes NoC.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Models for Embedded Application Mapping onto NoCs: Timing Analysis.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

Energy and latency evaluation of NoC topologies.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique.
Proceedings of the 2005 Design, 2005

MAIA: a framework for networks on chip generation and verification.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
HERMES: an infrastructure for low area overhead packet-switching networks on chip.
Integr., 2004

PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systems.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications.
Proceedings of the Field Programmable Logic and Application, 2004

MultiNoC: A Multiprocessing System Enabled by a Network on Chip.
Proceedings of the 2004 Design, 2004

2003
A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping.
Proceedings of the IFIP VLSI-SoC 2003, 2003

From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Remote and Partial Reconfiguration of FPGAs: Tools and Trends.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs.
Proceedings of the 2003 Design, 2003

2002
Prototyping of embedded digital systems from SDL language: a case study.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

2001
Integrating the teaching of computer organization and architecture with digital hardware design early in undergraduate courses.
IEEE Trans. Educ., 2001

Projeto para Prototipação de um IP Soft Core MAC Ethernet.
RITA, 2001

1994
Boolean constrained encoding: a new formulation and a case study.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994


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