Weizhe Hua

According to our database, Weizhe Hua authored at least 23 papers between 2016 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

Information Flow Control in Machine Learning through Modular Model Architecture.

Trishita Tiwari, Suchin Gururangan, Chuan Guo, Weizhe Hua, Sanjay Kariyappa, Udit Gupta, Wenjie Xiong, Kiwan Maeng, Hsien-Hsin S. Lee, G. Edward Suh

CoRR, 2023

2022

Reverse-Engineering CNN Models Using Side-Channel Attacks.

Weizhe Hua, Zhiru Zhang, G. Edward Suh

IEEE Des. Test, 2022

Structured Pruning is All You Need for Pruning CNNs at Initialization.

Yaohui Cai, Weizhe Hua, Hongzheng Chen, G. Edward Suh, Christopher De Sa, Zhiru Zhang

CoRR, 2022

SoftVN: efficient memory protection via software-provided version numbers.

Muhammad Umar, Weizhe Hua, Zhiru Zhang, G. Edward Suh

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

MGX: near-zero overhead memory protection for data-intensive accelerators.

Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

Transformer Quality in Linear Time.

Weizhe Hua, Zihang Dai, Hanxiao Liu, Quoc V. Le

Proceedings of the International Conference on Machine Learning, 2022

GuardNN: secure accelerator architecture for privacy-preserving deep learning.

Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Sinan: Data Driven Resource Management for Cloud Microservices.

Yanqi Zhang, Weizhe Hua, Zhuangzhuang Zhou, G. Edward Suh, Christina Delimitrou

CoRR, 2021

Sinan: Data-Driven, QoS-Aware Cluster Management for Microservices.

Yanqi Zhang, Weizhe Hua, Zhuangzhuang Zhou, G. Edward Suh, Christina Delimitrou

CoRR, 2021

BulletTrain: Accelerating Robust Neural Network Training via Boundary Example Mining.

Weizhe Hua, Yichi Zhang, Chuan Guo, Zhiru Zhang, G. Edward Suh

Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021

Sinan: ML-based and QoS-aware resource management for cloud microservices.

Yanqi Zhang, Weizhe Hua, Zhuangzhuang Zhou, G. Edward Suh, Christina Delimitrou

Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

2020

Contrastive Weight Regularization for Large Minibatch SGD.

Qiwei Yuan, Weizhe Hua, Yi Zhou, Cunxi Yu

CoRR, 2020

GuardNN: Secure DNN Accelerator for Privacy-Preserving Deep Learning.

Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh

CoRR, 2020

MgX: Near-Zero Overhead Memory Protection with an Application to Secure DNN Acceleration.

Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh

CoRR, 2020

Precision Gating: Improving Neural Network Efficiency with Dynamic Dual-Precision Activations.

Yichi Zhang, Ritchie Zhao, Weizhe Hua, Nayun Xu, G. Edward Suh, Zhiru Zhang

Proceedings of the 8th International Conference on Learning Representations, 2020

2019

Channel Gating Neural Networks.

Weizhe Hua, Yuan Zhou, Christopher De Sa, Zhiru Zhang, G. Edward Suh

Proceedings of the Advances in Neural Information Processing Systems 32: Annual Conference on Neural Information Processing Systems 2019, 2019

Boosting the Performance of CNN Accelerators with Dynamic Fine-Grained Channel Gating.

Weizhe Hua, Yuan Zhou, Christopher De Sa, Zhiru Zhang, G. Edward Suh

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

2018

Channel Gating Neural Networks.

Weizhe Hua, Christopher De Sa, Zhiru Zhang, G. Edward Suh

CoRR, 2018

Reverse engineering convolutional neural networks through side-channel information leaks.

Weizhe Hua, Zhiru Zhang, G. Edward Suh

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

Secure Information Flow Verification with Mutable Dependent Types.

Andrew Ferraiuolo, Weizhe Hua, Andrew C. Myers, G. Edward Suh

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI.

Ramy N. Tadros, Weizhe Hua, Matheus T. Moreira, Ney Laert Vilar Calazans, Peter A. Beerel

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Low Area, Low Power, Robust, Highly Sensitive Error Detecting Latch for Resilient Architectures.

Weizhe Hua, Ramy N. Tadros, Peter A. Beerel

Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications.

Ramy N. Tadros, Weizhe Hua, Matheus Gibiluka, Matheus T. Moreira, Ney Laert Vilar Calazans, Peter A. Beerel

Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016