Matheus T. Moreira

According to our database1, Matheus T. Moreira authored at least 77 papers between 2008 and 2021.

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Bibliography

2021
A High-Level Modeling Framework for Estimating Hardware Metrics of CNN Accelerators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A TensorFlow and System Simulator Integration Approach to Estimate Hardware Metrics of Convolution Accelerators.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

Quasi Delay Insensitive FIFOs: Design Choices Exploration and Comparison.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
A Survey of Aging Monitors and Reconfiguration Techniques.
CoRR, 2020

Leveraging QDI Robustness to Simplify the Design of IoT Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A Frontend using Traditional EDA Tools for the Pulsar QDI Design Flow.
Proceedings of the 26th IEEE International Symposium on Asynchronous Circuits and Systems, 2020

Chronos Link: A QDI Interconnect for Modern SoCs.
Proceedings of the 26th IEEE International Symposium on Asynchronous Circuits and Systems, 2020

Test Oriented Design and Layout Generation of an Asynchronous Controller for the Blade Template.
Proceedings of the 26th IEEE International Symposium on Asynchronous Circuits and Systems, 2020

2019
Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools.
Proceedings of the 25th IEEE International Symposium on Asynchronous Circuits and Systems, 2019

2018
A DfT Insertion Methodology to Scannable Q-Flop Elements.
IEEE Trans. Very Large Scale Integr. Syst., 2018

NCL Synthesis With Conventional EDA Tools: Technology Mapping and Optimization.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Libra: An Automatic Design Methodology for CMOS Complex Gates.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Testable Error Detection Logic Design Applied to an Asynchronous Timing Resilient Template.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

An LSSD Compliant Scan Cell for Flip-Flops.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Optimized Design of an LSSD Scan Cell.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Sleep convention logic isochronic fork: an analysis.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Estimation methods for static noise margins in CMOS subthreshold logic circuits.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Transistor placement strategies for non-series-parallel cells.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A comparison of asynchronous QDI templates using static logic.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Post-processing of supergate networks aiming cell layout optimization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A post-processing methodology to improve the automatic design of CMOS gates at layout-level.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Hardening C-elements against metastability.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

2016
Asynchronous circuits: innovations in components, cell libraries and design templates.
PhD thesis, 2016

Testable MUTEX Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A processor for IoT applications: An assessment of design space and trade-offs.
Microprocess. Microsystems, 2016

A Fine-Grain, Uniform, Energy-Efficient Delay Element for 2-Phase Bundled-Data Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2016

A standard cell characterization flow for non-standard voltage supplies.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

Design and analysis of the HF-RISC processor targeting voltage scaling applications.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

Toward better layout design in ASTRAN CAD tool by using an efficient transistor folding.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

Optimizing cell area by applying an alternative transistor folding technique in an open source physical synthesis CAD tool.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

The HF-RISC processor: Performance assessment.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

ASCEnD-FreePDK45: An open source standard cell library for asynchronous design.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications.
Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016

2015
Static Differential NCL Gates: Toward Low Power.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits.
Proceedings of the 28th International Conference on VLSI Design, 2015

SDDS-NCL Design: Analysis of Supply Voltage Scaling.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

A digitally controlled oscillator for fine-grained local clock generators in MPSoCs.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

BAT-Hermes: A transition-signaling bundled-data NoC router.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

TDTB error detecting latches: Timing violation sensitivity analysis and optimization.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Design and Analysis of Testable Mutual Exclusion Elements.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

Blade - A Timing Violation Resilient Asynchronous Template.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

Performance Optimization and Analysis of Blade Designs under Delay Variability.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

2014
Beware the Dynamic C-Element.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Spatially Distributed Dual-Spacer Null Convention Logic Design.
J. Low Power Electron., 2014

Advances on the state of the art in QDI design.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Automated Synthesis of Cell Libraries for Asynchronous Circuits.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

Schmitt trigger on output inverters of NCL gates for soft error hardening: Is it enough?
Proceedings of the 15th Latin American Test Workshop, 2014

Automatic layout synthesis with ASTRAN applied to asynchronous cells.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

A design flow for physical synthesis of digital cells with ASTRAN.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Hardening QDI circuits against transient faults using delay-insensitive maxterm synthesis.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014

A New CMOS Topology for Low-Voltage Null Convention Logic Gates Design.
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014

2013
Lasio 3D NoC vertical links serialization: Evaluation of latency and buffer occupancy.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

BaBaNoC: An asynchronous network-on-chip described in Balsa.
Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013

NCL+: Return-to-one Null Convention Logic.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Design of NCL gates with the ASCEnD flow.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Design of standard-cell libraries for asynchronous circuits with the ASCEnD flow.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Evaluating the scalability of test buses.
Proceedings of the 2013 International Symposium on System on Chip, 2013

Voltage scaling on C-elements: A speed, power and energy efficiency analysis.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell Libraries.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Charge sharing aware NCL gates design.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2012
Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

Impact of C-elements in asynchronous circuits.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Return-to-One DIMS logic on 4-phase m-of-n asynchronous circuits.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Electrical characterization of a C-Element with LiChEn.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

A generic FPGA emulation framework.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
A 65nm standard cell set and flow dedicated to automated asynchronous circuits design.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Adapting a C-element design flow for low power.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010
Hermes-AA: A 65nm asynchronous NoC router with adaptive routing.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Hermes-A - An Asynchronous NoC Router with Distributed Routing.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

2008
Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008


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