Rance Rodrigues

According to our database1, Rance Rodrigues authored at least 27 papers between 2009 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2015
Does the Sharing of Execution Units Improve Performance/Power of Multicores?
ACM Trans. Embed. Comput. Syst., 2015

A Hardware Framework for Yield and Reliability Enhancement in Chip Multiprocessors.
ACM Trans. Embed. Comput. Syst., 2015

2014
A low-power instruction replay mechanism for design of resilient microprocessors.
ACM Trans. Embed. Comput. Syst., 2014

Performance and Power Benefits of Sharing Execution Units between a High Performance Core and a Low Power Core.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Reducing Energy per Instruction via Dynamic Resource Allocation and Voltage and Frequency Adaptation in Asymmetric Multicores.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

A runtime support mechanism for fast mode switching of a self-morphing core for power efficiency.
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

2013
A Study on the Use of Performance Counters to Estimate Power in Microprocessors.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

A study on polymorphing superscalar processor dynamically to improve power efficiency.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

On dynamic polymorphing of a superscalar core for improving energy efficiency.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

A low power architecture for online detection of execution errors in SMT processors.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

An opportunistic prediction-based thread scheduling to maximize throughput/watt in AMPs.
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012
Improving performance per watt of asymmetric multi-core processors via online program phase classification and adaptive core morphing.
ACM Trans. Design Autom. Electr. Syst., 2012

Scalable Thread Scheduling in Asymmetric Multicores for Power Efficiency.
Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012

Dynamic Thread Scheduling in Asymmetric Multicores to Maximize Performance-per-Watt.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

A mechanism to verify cache coherence transactions in multicore systems.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011
Model based double patterning lithography (DPL) and simulated annealing (SA).
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

On graceful degradation of chip multiprocessors in presence of faults via flexible pooling of critical execution units.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

On graceful degradation of microprocessors in presence of faults via resource banking.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

An Architecture to Enable Life Cycle Testing in CMPs.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

An Online Mechanism to Verify Datapath Execution Using Existing Resources in Chip Multiprocessors.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

An Architecture to Enable Lifetime Full Chip Testability in Chip Multiprocessors.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

Performance Per Watt Benefits of Dynamic Core Morphing in Asymmetric Multicores.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
Optical Lithography Simulation with Focus Variation using Wavelet Transform.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Shadow checker (SC): A low-cost hardware scheme for online detection of faults in small memory structures of a microprocessor.
Proceedings of the 2011 IEEE International Test Conference, 2010

A study on performance benefits of core morphing in an asymmetric multicore processor.
Proceedings of the 28th International Conference on Computer Design, 2010

A mask double patterning technique using litho simulation by wavelet transform.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009
Optical lithography simulation using wavelet transform.
Proceedings of the 27th International Conference on Computer Design, 2009


  Loading...