Ravi Patel

Affiliations:
  • University of Rochester, Department of Electrical and Computer Engineering, Rochester, NY, USA


According to our database1, Ravi Patel authored at least 12 papers between 2012 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2018
Exploratory design of on-chip power delivery for 14, 10, and 7 nm and beyond FinFET ICs.
Integr., 2018

2016
Reducing Switching Latency and Energy in STT-MRAM Caches With Field-Assisted Writing.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Power noise in 14, 10, and 7 nm FinFET CMOS technologies.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Exploratory Power Noise Models of Standard Cell 14, 10, and 7 nm FinFET ICs.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015
Multistate Register Based on Resistive RAM.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Resistive Ternary Content Addressable Memory Systems for Data-Intensive Computing.
IEEE Micro, 2015

2014
2T-1R STT-MRAM memory cells for enhanced on/off current ratio.
Microelectron. J., 2014

Sub-crosspoint RRAM decoding for improved area efficiency.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

Field driven STT-MRAM cell for reduced switching latency and energy.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
AC-DIMM: associative computing with STT-MRAM.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

2012
Arithmetic encoding for memristive multi-bit storage.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

STT-MRAM memory cells with enhanced on/off ratio.
Proceedings of the IEEE 25th International SOC Conference, 2012


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