Xiaochen Guo

Orcid: 0000-0001-7704-0412

According to our database1, Xiaochen Guo authored at least 35 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2024
Framework and Methods of State Monitoring-Based Positioning System on WIFI-RTT Clock Drift Theory.
IEEE Trans. Aerosp. Electron. Syst., February, 2024

2023
Precise and Efficient Patch Presence Test for Android Applications against Code Obfuscation.
Proceedings of the 32nd ACM SIGSOFT International Symposium on Software Testing and Analysis, 2023

Detecting JVM JIT Compiler Bugs via Exploring Two-Dimensional Input Spaces.
Proceedings of the 45th IEEE/ACM International Conference on Software Engineering, 2023

HIRAC: A Hierarchical Accelerator with Sorting-based Packing for SpGEMMs in DNN Applications.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

2022
ASA: Accelerating Sparse Accumulation in Column-wise SpGEMM.
ACM Trans. Archit. Code Optim., 2022

Emerging monolithic 3D integration: Opportunities and challenges from the computer system perspective.
Integr., 2022

Radio Frequency Fingerprint Identification Based on Logarithmic Power Cosine Spectrum.
IEEE Access, 2022

Optimizing Recurrent Spiking Neural Networks with Small Time Constants for Temporal Tasks.
Proceedings of the ICONS 2022: International Conference on Neuromorphic Systems, Knoxville, TN, USA, July 27, 2022

2021
DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect.
IEEE Trans. Very Large Scale Integr. Syst., 2021

SPX64: A Scratchpad Memory for General-purpose Microprocessors.
ACM Trans. Archit. Code Optim., 2021

Understanding the Impact of Neural Variations and Random Connections on Inference.
Frontiers Comput. Neurosci., 2021

An In-Memory Analog Computing Co-Processor for Energy-Efficient CNN Inference on Mobile Devices.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Temporal Learning with Biologically Fitted SNN Models.
Proceedings of the ICONS 2021: International Conference on Neuromorphic Systems 2021, 2021

Efficient and Accurate Computational Model of Neuron with Spike Frequency Adaptation.
Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021

2020
Scrabble: A Fine-Grained Cache with Adaptive Merged Block.
IEEE Trans. Computers, 2020

RnR: A Software-Assisted Record-and-Replay Hardware Prefetcher.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 Cache.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

ECC Cache: A Lightweight Error Detection for Phase-Change Memory Stuck-At Faults.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

SIP: Boosting Up Graph Computing by Separating the Irregular Property Data.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Stealing Your Data from Compressed Machine Learning Models.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Content Aware Refresh: Exploiting the Asymmetry of DRAM Retention Errors to Reduce the Refresh Frequency of Less Vulnerable Data.
IEEE Trans. Computers, 2019

Inference with Hybrid Bio-hardware Neural Networks.
CoRR, 2019

ClusCross: a new topology for silicon interposer-based network-on-chip.
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

Flow mapping and data distribution on mesh-based deep learning accelerator.
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

2018
Sanitizer: Mitigating the Impact of Expensive ECC Checks on STT-MRAM Based Main Memories.
IEEE Trans. Computers, 2018

A Supervised Stdp-Based Training Algorithm for Living Neural Networks.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

2017
Long short term memory based hardware prefetcher: a case study.
Proceedings of the International Symposium on Memory Systems, 2017

A study of unnecessary write backs.
Proceedings of the International Symposium on Memory Systems, 2017

Enabling efficient fine-grained DRAM activations with interleaved I/O.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

2016
Reducing Switching Latency and Energy in STT-MRAM Caches With Field-Assisted Writing.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Languages Must Expose Memory Heterogeneity.
Proceedings of the Second International Symposium on Memory Systems, 2016

2015
Resistive Ternary Content Addressable Memory Systems for Data-Intensive Computing.
IEEE Micro, 2015

2013
AC-DIMM: associative computing with STT-MRAM.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

2011
A resistive TCAM accelerator for data-intensive computing.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

2010
Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010


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