Riccardo Della Sala

Francesco Centurelli

IEEE Access, 2024

2023

A Novel FPGA Implementation of the NAND-PUF with Minimal Resource Usage and High Reliability.

[BibT_eX]

[DOI]

Cryptogr., June, 2023

A body-driven rail-to-rail 0.3 V operational transconductance amplifier exploiting current gain stages.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., May, 2023

An Improved Strong Arm Comparator With Integrated Static Preamplifier.

[BibT_eX]

[DOI]

IEEE Access, 2023

Exploiting the DD-Cell as an Ultra-Compact Entropy Source for an FPGA-Based Re-Configurable PUF-TRNG Architecture.

[BibT_eX]

[DOI]

IEEE Access, 2023

A 0.3V Rail-to-Rail Three-Stage OTA With High DC Gain and Improved Robustness to PVT Variations.

[BibT_eX]

[DOI]

IEEE Access, 2023

Robust Body Biasing Techniques for Dynamic Comparators.

[BibT_eX]

[DOI]

Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023

A Novel Ultra-Low Voltage Fully Synthesizable Comparator exploiting NAND Gates.

[BibT_eX]

[DOI]

Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023

A 2.5 GHz, 0.6 V Body Driven Dynamic Comparator Exploiting Charge Pump Based Dynamic Biasing.

[BibT_eX]

[DOI]

Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023

On Enhancing the Throughput of the Latched Ring Oscillator TRNG on FPGA.

[BibT_eX]

[DOI]

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023

2022

Enabling ULV Fully Synthesizable Analog Circuits: The BA Cell, a Standard-Cell-Based Building Block for Analog Design.

[BibT_eX]

[DOI]

Francesco Centurelli

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Lightweight FPGA Compatible Weak-PUF Primitive Based on XOR Gates.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Novel Ultra-Compact FPGA-Compatible TRNG Architecture Exploiting Latched Ring Oscillators.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

High-Throughput FPGA-Compatible TRNG Architecture Exploiting Multistimuli Metastable Cells.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A Novel Differential to Single-Ended Converter for Ultra-Low-Voltage Inverter-Based OTAs.

[BibT_eX]

[DOI]

Francesco Centurelli

IEEE Access, 2022

The DD-Cell: a Double Side Entropic Source exploitable as PUF and TRNG.

[BibT_eX]

[DOI]

Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022

Sub-μW Front-End Low Noise Amplifier for Neural Recording Applications.

[BibT_eX]

[DOI]

Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022

High-efficiency 0.3V OTA in CMOS 130nm technology using current mirrors with gain.

[BibT_eX]

[DOI]

Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022

2021

A Novel Ultra-Compact FPGA PUF: The DD-PUF.

[BibT_eX]

[DOI]

Cryptogr., 2021

SC-DDPL as a Countermeasure against Static Power Side-Channel Attacks.

[BibT_eX]

[DOI]

Cryptogr., 2021

2019

Area-Efficient Low-Power Bandpass Gm-C Filter for Epileptic Seizure Detection in 130nm CMOS.

[BibT_eX]

[DOI]

Pietro Monsurrò