Francesco Centurelli
Orcid: 0000-0003-3880-2546
According to our database1,
Francesco Centurelli
authored at least 73 papers
between 1998 and 2024.
Collaborative distances:
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Bibliography
2024
Rail to Rail ICMR and High Performance ULV Standard-Cell-Based Comparator for Biomedical and IoT Applications.
IEEE Access, 2024
A Novel High Performance Standard-Cell Based ULV OTA Exploiting an Improved Basic Amplifier.
IEEE Access, 2024
2023
Int. J. Circuit Theory Appl., November, 2023
High-Accuracy Low-Cost Generalized Complex Pruned Volterra Models for Nonlinear Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2023
A body-driven rail-to-rail 0.3 V operational transconductance amplifier exploiting current gain stages.
Int. J. Circuit Theory Appl., May, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023
IEEE Access, 2023
A 0.3V Rail-to-Rail Three-Stage OTA With High DC Gain and Improved Robustness to PVT Variations.
IEEE Access, 2023
A Novel Parallel Digitizer With a Pulseless Mixing-Filtering-Processing Architecture and Its Implementation in a SiGe HBT Technology at 40GS/s.
IEEE Access, 2023
Proceedings of the 19th International Conference on Synthesis, 2023
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023
A 2.5 GHz, 0.6 V Body Driven Dynamic Comparator Exploiting Charge Pump Based Dynamic Biasing.
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023
Proceedings of the International Workshop on Biomedical Applications, 2023
2022
IEEE Trans. Instrum. Meas., 2022
Enabling ULV Fully Synthesizable Analog Circuits: The BA Cell, a Standard-Cell-Based Building Block for Analog Design.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A SiGe HBT 6th-Order 10 GHz Inductor-Less Anti-Aliasing Low-Pass Filter for High-Speed ATI Digitizers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A Novel Differential to Single-Ended Converter for Ultra-Low-Voltage Inverter-Based OTAs.
IEEE Access, 2022
A Biasing Approach to Design Ultra-Low-Power Standard-Cell-Based Analog Building Blocks for Nanometer SoCs.
IEEE Access, 2022
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022
2021
A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-Flops.
IEEE Trans. Very Large Scale Integr. Syst., 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Design of Low-Voltage Power Efficient Frequency Dividers in Folded MOS Current Mode Logic.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Open J. Circuits Syst., 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
Microelectron. J., 2020
An improved reversed miller compensation technique for three-stage CMOS OTAs with double pole-zero cancellation and almost single-pole frequency response.
Int. J. Circuit Theory Appl., 2020
Low-power class-AB 4th-order low-pass filter based on current conveyors with dynamic mismatch compensation of biasing errors.
Int. J. Circuit Theory Appl., 2020
0.6-V CMOS cascode OTA with complementary gate-driven gain-boosting and forward body bias.
Int. J. Circuit Theory Appl., 2020
2019
High-gain, high-CMRR class AB operational transconductance amplifier based on the flipped voltage follower.
Int. J. Circuit Theory Appl., 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
2017
On the use of voltage conveyors for the synthesis of biquad filters and arbitrary networks.
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
2016
Comparative performance analysis and complementary triode based CMFB circuits for fully differential class AB symmetrical OTAs with low power consumption.
Int. J. Circuit Theory Appl., 2016
Proceedings of the 2016 MIXDES, 2016
2015
Design and validation through a frequency-based metric of a new countermeasure to protect nanometer ICs from side-channel attacks.
J. Cryptogr. Eng., 2015
2014
Microelectron. J., 2014
Design of broad-band power amplifiers by means of an impedance transforming lossy equalizer.
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014
2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
2012
Efficient Digital Background Calibration of Time-Interleaved Pipeline Analog-to-Digital Converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
2009
IEEE Trans. Circuits Syst. II Express Briefs, 2009
2008
EURASIP J. Adv. Signal Process., 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
IEEE Trans. Circuits Syst. II Express Briefs, 2007
A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
A Sample-and-Hold Circuit with Very Low Gain Error for Time Interleaving Applications.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Validation of a statistical non-linear model of GaAs HEMT MMIC's by hypothesis testing and principal components analysis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
A 10-Gb/s CMU/CDR chip-set in SiGe BiCMOS commercial technology with multistandard capability.
IEEE Trans. Very Large Scale Integr. Syst., 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
A high-speed low-voltage phase detector for clock recovery from NRZ data.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Robust three-state PFD architecture with enhanced frequency acquisition capabilities.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
2002
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
2000
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
1998
A monolithic 2.5-Gb/s clock and data recovery circuit based on Silicon bipolar technology.
Proceedings of the Broadband European Networks and Multimedia Services, 1998