Robert B. Reese

According to our database1, Robert B. Reese authored at least 18 papers between 1993 and 2015.

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Bibliography

2015
CE2016 steering committee: a short update.
Inroads, 2015

CE2016: Updated computer engineering curriculum guidelines.
Proceedings of the 2015 IEEE Frontiers in Education Conference, 2015

2014
Setting the stage for CE2016: A revised body of knowledge.
Proceedings of the IEEE Frontiers in Education Conference, 2014

2012
Uncle - An RTL Approach to Asynchronous Design.
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012

2007
Finite State Machine Datapath Design, Optimization, and Implementation
Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, ISBN: 978-3-031-79776-7, 2007

2006
Introduction to Logic Synthesis using Verilog HDL
Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, ISBN: 978-3-031-79743-9, 2006

2005
Early evaluation for performance enhancement in phased logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

A Coarse-Grain Phased Logic CPU.
IEEE Trans. Computers, 2005

2004
Cooperative and progressive design experience for embedded systems.
IEEE Trans. Educ., 2004

Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

2003
A Fine-Grain Phased Logic CPU.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

PLFire: A Visualization Tool for Asynchronous Phased Logic Designs.
Proceedings of the 2003 Design, 2003

2002
Generalized Early Evaluation in Self-Timed Circuits.
Proceedings of the 2002 Design, 2002

2001
Arithmetic Logic Circuits Using Self-Timed Bit Level Dataflow and Early Evaluation.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

2000
OpenDesign: An Open User-Configurable Project Environment for Collaborative Design and Execution on the Internet.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

1999
User-configurable experimental design flows on the web: the ISCAS'99 experiments.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1997
Developing and Distributing Component-Level VHDL Models.
J. VLSI Signal Process., 1997

1993
A Comparison of Synchronous and Asynchronous FSMD Designs.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993


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