Roland Dobai

Jan Korenek

Appl. Soft Comput., 2017

Designing bent boolean functions with parallelized linear genetic programming.

[BibT_eX]

[DOI]

Jakub Husa

Proceedings of the Genetic and Evolutionary Computation Conference, 2017

Evolutionary design of hash functions for IP address hashing using genetic programming.

[BibT_eX]

[DOI]

Marek Kidon

Proceedings of the 2017 IEEE Congress on Evolutionary Computation, 2017

2016

Adaptive development of hash functions in FPGA-based network routers.

[BibT_eX]

[DOI]

Jan Korenek

Proceedings of the 2016 IEEE Symposium Series on Computational Intelligence, 2016

2015

Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2015

Evolution of Non-Cryptographic Hash Function Pairs for FPGA-Based Network Applications.

[BibT_eX]

[DOI]

Jan Korenek

Proceedings of the IEEE Symposium Series on Computational Intelligence, 2015

2014

Evolutionary digital circuit design with fast candidate solution establishment in field programmable gate arrays.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Evolvable Systems, 2014

Evolutionary on-line synthesis of hardware accelerators for software modules in reconfigurable embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013

SAT-based generation of compressed skewed-load tests for transition delay faults.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2013

Compressed Skewed-Load Delay Test Generation Based on Evolution and Deterministic Initialization of Populations.

[BibT_eX]

[DOI]

Comput. Informatics, 2013

Towards evolvable systems based on the Xilinx Zynq platform.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Conference on Evolvable Systems, 2013

Image filter evolution on the Xilinx Zynq Platform.

[BibT_eX]

[DOI]

Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

2012

Automated Generation of Built-In Self-Repair Architectures for Random Logic SoC Cores.

[BibT_eX]

[DOI]

Mária Fischerová

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Genetic method for compressed skewed-load delay test generation.

[BibT_eX]

[DOI]

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011

A novel automatic test pattern generator for asynchronous sequential digital circuits.

[BibT_eX]

[DOI]

Microelectron. J., 2011

2010

Deductive Fault Simulation Technique for Asynchronous Circuits.

[BibT_eX]

[DOI]

Comput. Informatics, 2010

Test pattern generation for the combinational representation of asynchronous circuits.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009

Deductive Fault Simulation for Asynchronous Sequential Circuits.

[BibT_eX]

[DOI]