Elena Gramatová

According to our database1, Elena Gramatová authored at least 19 papers between 1993 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
A new method for path criticality calculation.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

A new user-friendly ATPG platform for digital circuits.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015
Parameterized Critical Path Selection for Delay Fault Testing.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2013
Delay Fault Coverage Increasing in Digital Circuits.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Redundancy algorithm for embedded memories with block-based architecture.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012
D&T Presenter - electronic interactive system for design and test education.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
A novel automatic test pattern generator for asynchronous sequential digital circuits.
Microelectron. J., 2011

Efficient diagnostics algorithms for regular computing structures.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2010
Deductive Fault Simulation Technique for Asynchronous Circuits.
Comput. Informatics, 2010

Test pattern generation for the combinational representation of asynchronous circuits.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009
Deductive Fault Simulation for Asynchronous Sequential Circuits.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Diagnosis of faulty units in regular graphs under the PMC model.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

2008
Boolean Formalisation of the PMC Model for Faulty Units Diagnosis in Regular Multi-Processor Systems.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2002
Hierarchical test generation for combinational circuits with real defects coverage.
Microelectron. Reliab., 2002

Integrated Design and Test Generation Under Internet Based Environment MOSCITO.
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

Internet-Based Collaborative Test Generation with MOSCITO.
Proceedings of the 2002 Design, 2002

2000
Hierarchical defect-oriented fault simulation for digital circuits.
Proceedings of the 5th European Test Workshop, 2000

1994
The MD5 Message-Digest Algorithm in the XILINX FPGA.
Proceedings of the Field-Programmable Logic, 1994

1993
REGGEN-Test pattern generation on register transfer level.
Proceedings of the European Design Automation Conference 1993, 1993


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