Roman Koch

According to our database1, Roman Koch authored at least 16 papers between 2002 and 2010.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2010
Path Heuristics Using ACO for Inter-domain Routing in Mobile Ad Hoc and Sensor Networks.
Proceedings of the Bio-Inspired Models of Network, Information, and Computing Systems, 2010

DynaCORE - Dynamically Reconfigurable Coprocessor for Network Processors.
Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010

2009
A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime.
Int. J. Reconfigurable Comput., 2009

2008
Adaptive Communication Architectures for Runtime Reconfigurable System-on-Chips.
Parallel Process. Lett., 2008

WCET determination tool for embedded systems software.
Proceedings of the 1st International Conference on Simulation Tools and Techniques for Communications, 2008

Performance Analysis of Bus-Based Interconnects for a Run-Time Reconfigurable Co-Processor Platform.
Proceedings of the 16th Euromicro International Conference on Parallel, 2008


On the design parameters of runtime reconfigurable systems.
Proceedings of the FPL 2008, 2008

Design and Simulation of Runtime Reconfigurable Systems.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2007
A Lightweight Framework for Runtime Reconfigurable System Prototyping.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

Communication Architectures for Dynamically Reconfigurable FPGA Designs.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

2006
DynaCORE - A Dynamically Reconfigurable Coprocessor Architecture for Network Processors.
Proceedings of the 14th Euromicro International Conference on Parallel, 2006

An adaptive system-on-chip for network applications.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Applying Partial Reconfiguration to Networks-On-Chips.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

A dynamically reconfigurable packet-switched network-on-chip.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2002
Systoles of a Family of Triangle Surfaces.
Exp. Math., 2002


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