Thilo Pionteck

According to our database1, Thilo Pionteck authored at least 79 papers between 2000 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
Optimising Operator Sets for Analytical Database Processing on FPGAs.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020

2019
Simulation environment for link energy estimation in networks-on-chip with virtual channels.
Integr., 2019

Crosstalk optimization for through-silicon vias by exploiting temporal signal misalignment.
Integr., 2019

Ratatoskr: An open-source framework for in-depth power, performance and area analysis in 3D NoCs.
CoRR, 2019

NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures.
IEEE Access, 2019

Area Optimization with Non-Linear Models in Core Mapping for System-on-Chips.
Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019

Survey on FPGAs in Medical Radiology Applications: Challenges, Architectures and Programming Models.
Proceedings of the International Conference on Field-Programmable Technology, 2019

System-Level Optimization of Network-on-Chips for Heterogeneous 3D System-on-Chips.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

2018
Cooking DBMS Operations using Granular Primitives - An Overview on a Primitive-based RDBMS Query Evaluation.
Datenbank-Spektrum, 2018

Integration of FPGAs in Database Management Systems: Challenges and Opportunities.
Datenbank-Spektrum, 2018

Specification of Simulation Models for NoCs in Heterogeneous 3D SoCs.
Proceedings of the 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018

Coding-aware Link Energy Estimation for 2D and 3D Networks-on-Chip with Virtual Channels.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Adaptive Data Processing in Heterogeneous Hardware Systems.
Proceedings of the 30th GI-Workshop Grundlagen von Datenbanken, Wuppertal, 2018

Efficient Inter-Kernel Communication for OpenCL Database Operators on FPGAs.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Hardware-Accelerated Index Construction for Semantic Web.
Proceedings of the International Conference on Field-Programmable Technology, 2018

2017
Semi-static operator graphs for accelerated query execution on FPGAs.
Microprocess. Microsystems, 2017

Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs.
Microprocess. Microsystems, 2017

Design method for asymmetric 3D interconnect architectures with high level models.
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017

Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

An FPGA-based prototyping framework for Networks-on-Chip.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

Continuous live-tracing as debugging approach on FPGAs.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

Hardware-Accelerated Radix-Tree Based String Sorting for Big Data Applications.
Proceedings of the Architecture of Computing Systems - ARCS 2017, 2017

2016
RAW 2014: Random Number Generators on FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2016

Runtime Adaptive Hybrid Query Engine based on FPGAs.
OJDB, 2016

Constructing Large-Scale Semantic Web Indices for the Six RDF Collation Orders.
OJBD, 2016

Accelerated join evaluation in Semantic Web databases by using FPGAs.
Concurr. Comput. Pract. Exp., 2016

A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

Hardware-accelerated pose estimation for embedded systems using Vivado HLS.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Adaptive allocation of default router paths in Network-on-Chips for latency reduction.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016

2015
PatTrieSort - External String Sorting based on Patricia Tries.
OJDB, 2015

Automated composition and execution of hardware-accelerated operator graphs.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

Hybrid FPGA approach for a B+ tree in a Semantic Web database system.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

An optimized radix-tree for hardware-accelerated dictionary generation for semantic web databases.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

An architectural template for composing application specific datapaths at runtime.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs.
Proceedings of the Nordic Circuits and Systems Conference, 2015

2014
Identifying homogenous reconfigurable regions in heterogeneous FPGAs for module relocation.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling.
Proceedings of the 2014 International Symposium on System-on-Chip, 2014

Influence of Magnetic Fields and X-Radiation on Ring Oscillators in FPGAs.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

Parallel and Pipelined Filter Operator for Hardware-Accelerated Operator Graphs in Semantic Web Databases.
Proceedings of the 14th IEEE International Conference on Computer and Information Technology, 2014

2013
Register allocation for high-level synthesis of hardware accelerators targeting FPGAs.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

Hardware-accelerated join processing in large Semantic Web databases with FPGAs.
Proceedings of the International Conference on High Performance Computing & Simulation, 2013

Prioritizing semi-static data streams in network-on-chips for runtime reconfigurable systems.
Proceedings of the International Conference on High Performance Computing & Simulation, 2013

2012
MONSUN II: A small and inexpensive AUV for underwater swarms.
Proceedings of the ROBOTIK 2012, 2012

An Approach for Performance Estimation of Hybrid Systems with FPGAs and GPUs as Coprocessors.
Proceedings of the Architecture of Computing Systems - ARCS 2012 - 25th International Conference, Munich, Germany, February 28, 2012

2011
Linking Formal Description and Simulation of Runtime Reconfigurable Systems.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

2010
Optimizing Runtime Reconfiguration Decisions.
Proceedings of the IEEE/IFIP 8th International Conference on Embedded and Ubiquitous Computing, 2010

A concept of a trust management architecture to increase the robustness of nano age devices.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28, 2010

DynaCORE - Dynamically Reconfigurable Coprocessor for Network Processors.
Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010

2009
A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime.
Int. J. Reconfigurable Comput., 2009

2008
Adaptive Communication Architectures for Runtime Reconfigurable System-on-Chips.
Parallel Process. Lett., 2008

WCET determination tool for embedded systems software.
Proceedings of the 1st International Conference on Simulation Tools and Techniques for Communications, 2008

Performance Analysis of Bus-Based Interconnects for a Run-Time Reconfigurable Co-Processor Platform.
Proceedings of the 16th Euromicro International Conference on Parallel, 2008


On the design parameters of runtime reconfigurable systems.
Proceedings of the FPL 2008, 2008

Design and Simulation of Runtime Reconfigurable Systems.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2007
Dynamically Reconfigurable Computing for Wireless Communication Systems (Dynamisch rekonfigurierbares Rechnen für Mobilfunksysteme).
it Inf. Technol., 2007

A Lightweight Framework for Runtime Reconfigurable System Prototyping.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

Teaching Informatics Students the Secrets of Hardware Design.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

Communication Architectures for Dynamically Reconfigurable FPGA Designs.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

2006
Eine Scheduling Heuristik zur Minimierung der Verlustleistung.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006

An adaptive system-on-chip for network applications.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Applying Partial Reconfiguration to Networks-On-Chips.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

A dynamically reconfigurable packet-switched network-on-chip.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques.
Proceedings of the Embedded Computer Systems: Architectures, 2005

Prozessorintegration und Speicheranbindung dynamisch rekonfigurierbarer Funktionseinheiten.
Proceedings of the 18th International Conference on Architecture of Computing Systems, 2005

2004
Design of a reconfigurable AES encryption/decryption engine for mobile terminals.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A Dynamically Reconfigurable Function-Unit for Error Detection and Correction in Mobile Terminals.
Proceedings of the Field Programmable Logic and Application, 2004

On the design of a function-specific reconfigurable: hardware accelerator for the MAC-layer in WLANs.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Reconfigurable platforms for ubiquitous computing.
Proceedings of the First Conference on Computing Frontiers, 2004

Integration dynamisch rekonfigurierbarer Funktionseinheiten in Prozessoren.
Proceedings of the ARCS 2004, 2004

2003
On the Rapid Prototyping of Equalizers for OFDM Systems.
Design Autom. for Emb. Sys., 2003

Exploring the Capabilities of Reconfigurable Hardware for OFDM-Based Wlans.
Proceedings of the VLSI-SOC: From Systems to Chips, 2003

The requirement for flexibility in IP-based designs increasesHardware Evaluation of Low Power Communication Mechanisms for Transport-Triggered Architectures.
Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003

Reconfiguration requirements for high speed wireless communication systems.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

2002
On the Rapid Prototyping of Equalizers for OFDM Systems.
Proceedings of the 13th IEEE International Workshop on Rapid System Prototyping (RSP 2002), 2002

A Framework for Teaching (Re)Configurable Architectures in Student Projects.
Proceedings of the Field-Programmable Logic and Applications, 2002

2001
Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures.
Proceedings of the Field-Programmable Logic and Applications, 2001

2000
DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communications Applications.
Proceedings of the Field-Programmable Logic and Applications, 2000


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