Carsten Albrecht

According to our database1, Carsten Albrecht authored at least 25 papers between 1999 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2011
Linking Formal Description and Simulation of Runtime Reconfigurable Systems.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

2010
Modellierung und Simulation dynamisch rekonfigurierbarer Architekturen am Beispiel eines laufzeitadaptiven Netzwerk-Coprozessors.
PhD thesis, 2010

Optimizing Runtime Reconfiguration Decisions.
Proceedings of the IEEE/IFIP 8th International Conference on Embedded and Ubiquitous Computing, 2010

DynaCORE - Dynamically Reconfigurable Coprocessor for Network Processors.
Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010

2009
A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime.
Int. J. Reconfig. Comp., 2009

2008
Adaptive Communication Architectures for Runtime Reconfigurable System-on-Chips.
Parallel Processing Letters, 2008

WCET determination tool for embedded systems software.
Proceedings of the 1st International Conference on Simulation Tools and Techniques for Communications, 2008

Performance Analysis of Bus-Based Interconnects for a Run-Time Reconfigurable Co-Processor Platform.
Proceedings of the 16th Euromicro International Conference on Parallel, 2008


On the design parameters of runtime reconfigurable systems.
Proceedings of the FPL 2008, 2008

Design and Simulation of Runtime Reconfigurable Systems.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2007
A Lightweight Framework for Runtime Reconfigurable System Prototyping.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

Communication Architectures for Dynamically Reconfigurable FPGA Designs.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

2006
DynaCORE - A Dynamically Reconfigurable Coprocessor Architecture for Network Processors.
Proceedings of the 14th Euromicro International Conference on Parallel, 2006

Impact of Coprocessors on a Multithreaded Processor Design Using Prioritized Threads.
Proceedings of the 14th Euromicro International Conference on Parallel, 2006

An adaptive system-on-chip for network applications.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Applying Partial Reconfiguration to Networks-On-Chips.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

A dynamically reconfigurable packet-switched network-on-chip.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Parallel Processing in Network Processor Architectures (Parallelverarbeitung in Netzwerkprozessorarchitekturen).
it - Information Technology, 2005

A Compiler for Mapping a Rule-Based Event-Triggered Program to a Hardware Engine.
Electr. Notes Theor. Comput. Sci., 2005

2004
RTeasy: an algorithmic design environment on register transfer level.
Proceedings of the 2004 workshop on Computer architecture education, 2004

Cooperative Software Multithreading to Enhance Utilization of Embedded Processors for Network Applications.
Proceedings of the 12th Euromicro Workshop on Parallel, 2004

A Comparison of Parallel Programming Models of Network Processors.
Proceedings of the ARCS 2004, 2004

1999
Tuning Message Aggregation on High Performance Clusters for Efficient Parallel Simulations.
Parallel Processing Letters, 1999

Optimizing Message Aggregation for Parallel Simulation on High Performance Clusters.
Proceedings of the MASCOTS 1999, 1999


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