H. Narayanan

According to our database, H. Narayanan authored at least 40 papers between 1990 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

On composition and decomposition operations for vector spaces, graphs and matroids.

H. Narayanan

CoRR, 2023

2021

On Thevenin-Norton and Maximum power transfer theorems.

H. Narayanan, Hariharan Narayanan

CoRR, 2021

Implicit Linear Algebra and Basic Circuit Theory II: port behaviour of rigid multiports.

H. Narayanan

CoRR, 2021

2020

Implicit Linear Algebra and Basic Circuit Theory.

H. Narayanan, Hariharan Narayanan

CoRR, 2020

2016

Relaxation Based Circuit Simulation Acceleration over CPU-FPGA.

Vinay B. Y. Kumar, Kulshreshth Dhiman, Mandar Datar, Akash Pacharne, H. Narayanan, Sachin B. Patkar

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2013

Solution of PDEs-electrically coupled systems with electrical analogy.

Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar

Integr., 2013

Memory Efficient Implementation of Two Graph Based Circuit Simulator for PDE-Electrical Analogy.

Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Hardware-software Scalable Architectures for Gaussian Elimination over GF(2) and Higher Galois Fields.

Prateek Saxena, Vinay B. Y. Kumar, Dilawar Singh, H. Narayanan, Sachin B. Patkar

Proceedings of the PECCS 2013, 2013

2012

Two Graph Based Circuit Simulator for PDE-Electrical Analogy.

Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar

Proceedings of the 25th International Conference on VLSI Design, 2012

2011

On the Use of Simple Electrical Circuit Techniques for Performance Modeling and Optimization in VLSI Systems.

Gautam Hazari, H. Narayanan

IEEE Trans. Very Large Scale Integr. Syst., 2011

Solution of Partial Differential Equations by electrical analogy.

Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar

J. Comput. Sci., 2011

2010

FPGA Based High Performance Double-Precision Matrix Multiplication.

Vinay B. Y. Kumar, Siddharth Joshi, Sachin B. Patkar, H. Narayanan

Int. J. Parallel Program., 2010

Large Scale VLSI Circuit Simulation Using Point Relaxation.

Subhendu Roy, Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar

Proceedings of the 2010 International Conference on Scientific Computing, 2010

2009

Exploiting Hybrid Analysis in Solving Electrical Networks.

V. Siva Sankar, H. Narayanan, Sachin B. Patkar

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

2007

Application of DC Analyzer to Combinatorial Optimization Problems.

Gaurav Trivedi, Sumit Punglia, H. Narayanan

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Parallelization of DC Analysis through Multiport Decomposition.

Gaurav Trivedi, Madhav P. Desai, H. Narayanan

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Application of Fast DC Analysis to Partitioning Hypergraphs.

Gaurav Trivedi, H. Narayanan

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

Fast DC Analysis and Its Application to Combinatorial Optimization Problems.

Gaurav Trivedi, Madhav P. Desai, H. Narayanan

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2004

Mathematical programming and resistor transformer diode networks.

H. Narayanan

Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

2003

Fast On-Line/Off-Line Algorithms for Optimal Reinforcement of a Network and its Connections with Principal Partition.

Sachin B. Patkar, H. Narayanan

J. Comb. Optim., 2003

Improving graph partitions using submodular functions.

Sachin B. Patkar, H. Narayanan

Discret. Appl. Math., 2003

A note on the minimization of symmetric and general submodular functions.

H. Narayanan

Discret. Appl. Math., 2003

The realization of finite state machines by decomposition and the principal lattice of partitions of a submodular function.

Madhav P. Desai, H. Narayanan, Sachin B. Patkar

Discret. Appl. Math., 2003

An Efficient Practical Heuristic For Good Ratio-Cut Partitioning.

Sachin B. Patkar, H. Narayanan

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

2002

Some applications of an Implicit Duality Theorem to connections of structures of special types including Dirac and reciprocal structures.

H. Narayanan

Syst. Control. Lett., 2002

On Duality of Behavioural Systems.

Harish K. Pillai, H. Narayanan

Multidimens. Syst. Signal Process., 2002

Mathematical Methods in VLSI (Tutorial Abstract).

M. V. Atre, P. S. Subramanian, H. Narayanan

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

2001

A note on optimal covering augmentation for graphic polymatroids.

Sachin B. Patkar, H. Narayanan

Inf. Process. Lett., 2001

Spectral Algorithm To Compute And Synthesize Reduced Order Passive Models For Arbitrary Rc Multiports.

Shabbir H. Batterywala, H. Narayanan

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

1999

A State Assignment Scheme Targeting Performance and Area.

B. N. V. Malleswara Gupta, H. Narayanan, Madhav P. Desai

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Efficient DC Analysis of RVJ Circuits for Moment and Derivative Commutations of Interconnect Networks.

Shabbir H. Batterywala, H. Narayanan

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Decomposition of Finite State Machines for Area, Delay Minimization.

Rupesh S. Shelar, Madhav P. Desai, H. Narayanan

Proceedings of the IEEE International Conference On Computer Design, 1999

1997

A New Partitioning Strategy Based on Supermodular Functions.

Sachin B. Patkar, Shabbir H. Batterywala, M. Chandramouli, H. Narayanan

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996

Approximation Algorithms for Min-k-Overlap Problems Using the Principal Lattice of Partitions Approach.

H. Narayanan, Subir K. Roy, Sachin B. Patkar

J. Algorithms, 1996

1994

Randomized Parallel Algorithms for Matroid Union and Intersection, With Applications to Arboresences and Edge-Disjoint Spanning Trees.

H. Narayanan, Huzur Saran, Vijay V. Vazirani

SIAM J. Comput., 1994

1993

Application of the principal partition and principal lattice of partitions of a graph to the problem of decomposition of a finite state machine.

Subir K. Roy, H. Narayanan

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1992

Principal Lattice of Partition of submodular functions on Graphs: Fast algorithms for Principal Partition and Generic Rigidity.

Sachin B. Patkar, H. Narayanan

Proceedings of the Algorithms and Computation, Third International Symposium, 1992

Fast Sequential and Randomised Parallel Algorithms for Rigidity and approximate Min k-cut.

Sachin B. Patkar, H. Narayanan

Proceedings of the Foundations of Software Technology and Theoretical Computer Science, 1992

1991

A Fast Algorithm for the Principle Partition of a Graph.

Sachin B. Patkar, H. Narayanan

Proceedings of the Foundations of Software Technology and Theoretical Computer Science, 1991

1990

On the minimum hybrid rank of a graph relative to a partition of its edges and its application to electrical network analysis.

H. Narayanan

Int. J. Circuit Theory Appl., 1990