Prashant Saxena

According to our database, Prashant Saxena authored at least 42 papers between 1994 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2022

An Accurate, Error-Tolerant, and Energy-Efficient Neural Network Inference Engine Based on SONOS Analog Memory.

T. Patrick Xiao, Ben Feinberg, Christopher H. Bennett, Vineet Agrawal, Prashant Saxena, Venkatraman Prabhakar, Krishnaswamy Ramkumar, Harsha Medu, Vijay Raghavan, Ramesh Chettuvetty, Sapan Agarwal, Matthew J. Marinella

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Computational bifurcation analysis of hyperelastic thin shells.

Zhaowei Liu, Andrew McBride, Abhishek Ghosh, Luca Heltai, Weicheng Huang, Tiantang Yu, Paul Steinmann, Prashant Saxena

CoRR, 2022

2021

On the Accuracy of Analog Neural Network Inference Accelerators.

T. Patrick Xiao, Ben Feinberg, Christopher H. Bennett, Venkatraman Prabhakar, Prashant Saxena, Vineet Agrawal, Sapan Agarwal, Matthew J. Marinella

CoRR, 2021

Vibration Analysis of Piezoelectric Kirchhoff-Love Shells based on Catmull-Clark Subdivision Surfaces.

Zhaowei Liu, Andrew McBride, Prashant Saxena, Luca Heltai, Yilin Qu, Paul Steinmann

CoRR, 2021

Image GPT with Super Resolution.

Bhumika Shah, Ankita Sinha, Prashant Saxena

Proceedings of the Intelligent Data Engineering and Analytics, 2021

2019

Aspects of Isogeometric Analysis with Catmull-Clark Subdivision Surfaces.

Zhaowei Liu, Andrew McBride, Prashant Saxena, Paul Steinmann

CoRR, 2019

2017

Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning.

Wei-Ting Jonas Chan, Pei-Hsin Ho, Andrew B. Kahng, Prashant Saxena

Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

2014

Aerie: flexible file-system interfaces to storage-class memory.

Haris Volos, Sanketh Nalli, Sankaralingam Panneerselvam, Venkatanathan Varadarajan, Prashant Saxena, Michael M. Swift

Proceedings of the Ninth Eurosys Conference 2014, 2014

2012

On pioneering nanometer-era routing problems.

Tong Gao, Prashant Saxena

Proceedings of the International Symposium on Physical Design, 2012

2011

Guest Editorial.

Prashant Saxena, Yao-Wen Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Multi-mode redundancy removal.

Stephen M. Plaza, Prashant Saxena, Thomas R. Shiple, Pei-Hsin Ho

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2010

Guest Editorial.

Gi-Joon Nam, Prashant Saxena

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2009

On improving optimization effectiveness in interconnect-driven physical synthesis.

Prashant Saxena, Vishal Khandelwal, Changge Qiao, Pei-Hsin Ho, J.-C. Lin, Mahesh A. Iyer

Proceedings of the 2009 International Symposium on Physical Design, 2009

2008

Estimation of Routing Congestion.

Rupesh S. Shelar, Prashant Saxena

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

2007

Routing Congestion in VLSI Circuits - Estimation and Optimization.

Prashant Saxena, Rupesh S. Shelar, Sachin S. Sapatnekar

Series on Integrated Circuits and Systems, Springer, ISBN: 978-0-387-48550-8, 2007

2006

Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints.

Rupesh S. Shelar, Prashant Saxena, Sachin S. Sapatnekar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

On controlling perturbation due to repeaters during quadratic placement.

Prashant Saxena

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

The scaling of interconnect buffer needs.

Prashant Saxena

Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

2005

A predictive distributed congestion metric with application to technology mapping.

Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

An efficient technology mapping algorithm targeting routing congestion under delay constraints.

Rupesh S. Shelar, Prashant Saxena, Xinning Wang, Sachin S. Sapatnekar

Proceedings of the 2005 International Symposium on Physical Design, 2005

A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation.

Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Net weighting to reduce repeater counts during placement.

Brent Goplen, Prashant Saxena, Sachin S. Sapatnekar

Proceedings of the 42nd Design Automation Conference, 2005

A perturbation-aware noise convergence methodology for high frequency microprocessors.

Prashant Saxena, Kumar N. Lalgudi, Hans J. Greub, Janet Meiling Wang Roveda

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Repeater scaling and its impact on CAD.

Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

A predictive distributed congestion metric and its application to technology mapping.

Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang

Proceedings of the 2004 International Symposium on Physical Design, 2004

The great interconnect buffering debate: are you a chicken or an ostrich?

Desmond Kirkpatrick, Peter J. Osler, Louis Scheffer, Prashant Saxena, Dennis Sylvester

Proceedings of the 2004 International Symposium on Physical Design, 2004

Modeling repeaters explicitly within analytical placement.

Prashant Saxena, Bill Halpin

Proceedings of the 41th Design Automation Conference, 2004

Realizable parasitic reduction for distributed interconnects using matrix pencil technique.

Janet Meiling Wang, Prashant Saxena, Omar Hafiz, Xing Wang

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Coupling delay optimization by temporal decorrelation using dual threshold voltage technique.

Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang

IEEE Trans. Very Large Scale Integr. Syst., 2003

On integrating power and signal routing for shield count minimization in congested regions.

Prashant Saxena, Satyanarayan Gupta

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

The scaling challenge: can correct-by-construction design help?

Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick

Proceedings of the 2003 International Symposium on Physical Design, 2003

2002

Shield count minimization in congested regions.

Prashant Saxena, Satyanarayan Gupta

Proceedings of 2002 International Symposium on Physical Design, 2002

A System-Level Solution to Domino Synthesis with 2 GHz Application.

B. Chappell, Xinning Wang, Priyadarsan Patra, Prashant Saxena, J. Vendrell, Satyanarayan Gupta, S. Varadarajan, W. Gomes, S. Hussain, H. Krishnamurthy, M. Venkateshmurthy, S. Jain

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

2001

Optimization of the maximum delay of global interconnects duringlayer assignment.

Prashant Saxena, C. L. Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique.

Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang

Proceedings of the 38th Design Automation Conference, 2001

2000

A postprocessing algorithm for crosstalk-driven wire perturbation.

Prashant Saxena, C. L. Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

1999

The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches.

Prashant Saxena, Peichen Pan, C. L. Liu

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Crosstalk Minimization Using Wire Perturbations.

Prashant Saxena, C. L. Liu

Proceedings of the 36th Conference on Design Automation, 1999

1998

The Retiming and Routing of VLSI Circuits

Prashant Saxena

PhD thesis, 1998

A performance-driven layer assignment algorithm for multiple interconnect trees.

Prashant Saxena, C. L. Liu

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1996

A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs.

Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu

Proceedings of the Euro-Par '96 Parallel Processing, 1996

1994

Efficient Management of Dynamic Tables.

Aviezri S. Fraenkel, Edward M. Reingold, Prashant Saxena

Inf. Process. Lett., 1994