Samad Sheikhaei
Orcid: 0000-0002-6221-7200
According to our database1,
Samad Sheikhaei
authored at least 35 papers
between 2005 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
Single-Inductor, Multiple-Input, Multiple-Output, DC-DC Converter Based on a New Software Zero-Current Switching Technique.
J. Circuits Syst. Comput., September, 2023
Image Interpolation Based on 2D-DWT with Novel Regularity-Preserving Algorithm Using RLS Adaptive Filters.
Int. J. Image Graph., September, 2023
A Novel, Software-Defined Control Method Using Sparsely Activated Microcontroller for Low-Power, Multiple-Input, Single-Inductor, Multiple-Output DC-DC Converters to Increase Efficiency.
IEEE Trans. Ind. Electron., 2023
2022
IEEE Trans. Ind. Electron., 2022
A Low-Power Logarithmic CMOS Digital-to-Analog Converter for Neural Signal Recording.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
J. Circuits Syst. Comput., 2022
2021
C3S-QVCO: A low phase noise low power super-harmonic coupling QVCO with cross-connected common-source nodes.
Microelectron. J., 2021
Microelectron. J., 2021
Hardware-Efficient Bartlett Spectral Density Estimator Based on Optimized R2<sup>2</sup>FFT Processor Using CCSSI Method.
J. Circuits Syst. Comput., 2021
Optimal sub-harmonic injection-locked MICS band transmitter for wireless CW-fNIRS systems.
Int. J. Circuit Theory Appl., 2021
Int. J. Circuit Theory Appl., 2021
Comput. Electr. Eng., 2021
2020
An O(1) time complexity sorting network for small number of inputs with hardware implementation.
Microprocess. Microsystems, 2020
1/f<sup>3</sup> (Close-in) Phase Noise Reduction by Tail Transistor Flicker Noise Suppression Technique.
J. Circuits Syst. Comput., 2020
A low-power, low-data-rate efficient ADC with hybrid exponential-linear transfer curve for bio-potential recording systems.
Int. J. Circuit Theory Appl., 2020
CoRR, 2020
2019
A low-power low-noise CMOS bio-potential amplifier for multi-channel neural recording with active DC-rejection and current sharing.
Microelectron. J., 2019
FPGA implementation of an adaptive window size image impulse noise suppression system.
J. Real Time Image Process., 2019
2018
A 60 mV Input Voltage, Process Tolerant Start-Up System for Thermoelectric Energy Harvesting.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A low phase noise super-harmonic coupling quadrature VCO using an additional double frequency oscillator.
Microelectron. J., 2018
Pseudo-impulse tail current shaping for phase noise reduction in CMOS LC oscillators.
Microelectron. J., 2018
2017
Phase noise reduction in a CMOS LC cross coupled oscillator using a novel tail current noise second harmonic filtering technique.
Microelectron. J., 2017
2015
A 0.8-V supply bulk-driven operational transconductance amplifier and Gm-C filter in 0.18 µm CMOS process.
Int. J. Circuit Theory Appl., 2015
2013
Design of a direct conversion ultra low power ZigBee receiver RF front-end for wireless sensor networks.
Microelectron. J., 2013
2012
Microelectron. J., 2012
2011
Digital Compensation Techniques for Frequency-Translating Hybrid Analog-to-Digital Converters.
IEEE Trans. Instrum. Meas., 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011
2010
A 4 GHz Non-Resonant Clock Driver With Inductor-Assisted Energy Return to Power Grid.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
2007
A 3GHz Switching DC-DC Converter Using Clock-Tree Charge-Recycling in 90nm CMOS with Integrated Output Filter.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005