Massoud Tohidian

According to our database1, Massoud Tohidian authored at least 16 papers between 2009 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2021
A fast settling frequency synthesizer with switched-bandwidth loop filter.
Int. J. Circuit Theory Appl., 2021

2018
A 0.49-13.3 MHz Tunable Fourth-Order LPF with Complex Poles Achieving 28.7 dBm OIP3.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2017
A Fully Integrated Discrete-Time Superheterodyne Receiver.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network.
IEEE J. Solid State Circuits, 2017

2016
Toward Solving Multichannel RF-SoC Integration Issues Through Digital Fractional Division.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Analysis and Design of a Multi-Core Oscillator for Ultra-Low Phase Noise.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A High IIP2 SAW-Less Superheterodyne Receiver With Multistage Harmonic Rejection.
IEEE J. Solid State Circuits, 2016

A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015
Analysis and Design of I/Q Charge-Sharing Band-Pass-Filter for Superheterodyne Receivers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A TDD/FDD SAW-less superheterodyne receiver with blocker-resilient band-pass filter and multi-stage HR in 28nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015

2014
Analysis and Design of a High-Order Discrete-Time Passive IIR Low-Pass Filter.
IEEE J. Solid State Circuits, 2014

3.8 A fully integrated highly reconfigurable discrete-time superheterodyne receiver.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
A 2mW 800MS/s 7th-order discrete-time IIR filter with 400kHz-to-30MHz BW and 100dB stop-band rejection in 65nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Frequency translation through fractional division for a two-channel pulling mitigation.
Proceedings of the ESSCIRC 2013, 2013

2011
High-swing class-C VCO.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

2009
A simplified method for phase noise calculation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009


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