Sang-Min Yoo

Orcid: 0000-0002-8429-2666

According to our database1, Sang-Min Yoo authored at least 19 papers between 2000 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A Temperature Compensated Ring Oscillator With LC-Based Period Error Detection.
IEEE Trans. Very Large Scale Integr. Syst., December, 2023

2021
A Quadrature Class-G Complex-Domain Doherty Digital Power Amplifier.
IEEE J. Solid State Circuits, 2021

2020
A Multimode Multi-Efficiency-Peak Digital Power Amplifier.
IEEE J. Solid State Circuits, 2020

24.4 A Watt-Level Multimode Multi-Efficiency-Peak Digital Polar Power Amplifier with Linear Single-Supply Class-G Technique.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

10.7 A 0.26mm<sup>2</sup> DPD-Less Quadrature Digital Transmitter With 30dB Pout Range in 65nm CMOS.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A Watt-Level Quadrature Class-G Switched-Capacitor Power Amplifier With Linearization Techniques.
IEEE J. Solid State Circuits, 2019

2013
A Class-G Switched-Capacitor RF Power Amplifier.
IEEE J. Solid State Circuits, 2013

2012
Digital power amplifier: A new way to exploit the switched-capacitor circuit.
IEEE Commun. Mag., 2012

2011
A Switched-Capacitor RF Power Amplifier.
IEEE J. Solid State Circuits, 2011

A switched-capacitor power amplifier for EER/polar transmitters.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Towards greener wireless transmission: Efficient power amplifier design.
Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

2006
A 15mW 0.2mm<sup>2</sup> 50MS/s ADC with wide input range.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 3.0V 12b 120 Msample/s CMOS pipelined ADC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 3.0 V 72mW 10b 100 MSample/s Nyquist-rate CMOS pipelined ADC in 0.54 mm<sup>2</sup>.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2004
A 2.5-V 10-b 120-MSample/s CMOS pipelined ADC based on merged-capacitor switching.
IEEE Trans. Circuits Syst. II Express Briefs, 2004

A 10-b 150-MSample/s 1.8-V 123-mW CMOS A/D converter with 400-MHz input bandwidth.
IEEE J. Solid State Circuits, 2004

2002
A 2.5 V 10 b 120 MSample/s CMOS pipelined ADC with high SFDR.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2000
Acquisition-time minimization and merged-capacitor switching techniques for sampling-rate and resolution improvement of CMOS ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A 12b 50 MHz 3.3V CMOS acquisition time minimized A/D converter.
Proceedings of ASP-DAC 2000, 2000


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