Jae-Whui Kim

According to our database¹, Jae-Whui Kim authored at least 29 papers between 2000 and 2009.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

Timeline

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In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2009

An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008

A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2008

A 16b 10MS/s digitally self-calibrated ADC with time constant control.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

A 65nm CMOS 1.2V 12b 30MS/s ADC with capacitive reference scaling.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

A 101-dB SNR hybrid delta-sigma audio ADC using post integration time control.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007

Slew-Rate-Controlled Output Driver Having Constant Transition Time Over Process, Voltage, Temperature, and Output Load Variations.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2007

A 14-b 30MS/s 0.75mm2 Pipelined ADC with On-Chip Digital Self-Calibration.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

A Re-configurable 0.5V to 1.2V, 10MS/s to 100MS/s, Low-Power 10b 0.13um CMOS Pipeline ADC.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

An All-Digital 90-Degree Phase-Shift DLL with Loop-Embedded DCC for 1.6Gbps DDR Interface.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

A 15mW 0.2mm2 50MS/s ADC with wide input range.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 3.0V 12b 120 Msample/s CMOS pipelined ADC.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 3.0 V 72mW 10b 100 MSample/s Nyquist-rate CMOS pipelined ADC in 0.54 mm2.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A versatile I/O with robust impedance calibration for various memory interfaces.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 4mW per-Channel 101dB-DR Stereo Audio DAC with Transformed Quantization Structure.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

A Calibration-Free 14b 70MS/s 3.3mm2 235mW 0.13um CMOS Pipeline ADC with High-Matching 3-D Symmetric Capacitors.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005

A new level-up shifter for high speed and wide range interface in ultra deep sub-micron.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A slew rate-controlled output driver having a constant transition time over the variations of process, voltage and temperature.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

A high current driving charge pump with current regulation method.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004

A new level shifter in ultra deep sub-micron for low to wide range voltage applications.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

A 1.8V 8-bit 250Msample/s Nyquist-rate CMOS pipelined ADC.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A 2W, 92% efficiency and 0.01% THD+N class-D audio power amplifier for mobile applications, based on the novel SCOM architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003

A CMOS 16-bit 20MSPS analog front end for scanner/MFP applications.

[BibT_eX]

[DOI]

Seung-Bin You

Jae-Whui Kim

Suki Kim

IEEE Trans. Consumer Electron., 2003

A slew-rate controlled output driver using PLL as compensation circuit.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2003

Digitally tuneable on-chip resistor in CMOS for high-speed data transmission.

[BibT_eX]

[DOI]

Kyoung-Hoi Koo

Jin-Ho Seo

Jae-Whui Kim

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2000

A 3.3 V 14-bit 10 MSPS calibration-free CMOS pipelined A/D converter.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A 1 mW 10-bit 500KSPS SAR A/D converter.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A 2.4 V, 12 mW stereo audio D/A converter with double sampling switching.

[BibT_eX]

[DOI]

Nam-Keal Kim

Wang-Seup Yeum

Jae-Whui Kim

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A DLL based 10-320 MHz clock synchronizer.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A 1.4 V 10-bit 20 MSPS pipelined A/D converter.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Jae-Whui Kim

Timeline

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On csauthors.net:

Bibliography

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