Santanu Sarma

According to our database1, Santanu Sarma authored at least 20 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2024
14.3 A 3nm Adaptive Clock Duty-Cycle Controller for Mitigating Aging-Induced Clock Duty-Cycle Distortion.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2017
Architecture and Cross-Layer Design Space Exploration.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

2016
Cyber-Physical-System-On-Chip (CPSoC): An Exemplar Self-Aware SoC and Smart Computing Platform.
PhD thesis, 2016

Toward Smart Embedded Systems: A Self-aware System-on-Chip (SoC) Perspective.
ACM Trans. Embed. Comput. Syst., 2016

SPARTA: runtime task allocation for energy efficient heterogeneous many-cores.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

Cross-layer virtual/physical sensing and actuation for resilient heterogeneous many-core SoCs.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Essence: Machine Learning Approaches to Scalable and Energy Efficient Sense-making for Internet-of-Things (IoT).
MSc thesis, 2015

Cross-Layer Exploration of Heterogeneous Multicore Processor Configurations.
Proceedings of the 28th International Conference on VLSI Design, 2015

Self-Aware Cyber-Physical Systems-on-Chip.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Cyberphysical-system-on-chip (CPSoC): a self-aware MPSoC paradigm with cross-layer virtual sensing and actuation.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

SmartBalance: a sensing-driven linux load balancer for energy efficiency of heterogeneous MPSoCs.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Run-DMC: Runtime dynamic heterogeneous multicore performance and power estimation for energy efficiency.
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

2014
FPGA emulation and prototyping of a cyberphysical-system-on-chip (CPSoC).
Proceedings of the 25nd IEEE International Symposium on Rapid System Prototyping, 2014

Minimal sparse observability of complex networks: Application to MPSoC sensor placement and run-time thermal estimation & tracking.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Sense-making from Distributed and Mobile Sensing Data: A Middleware Perspective.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

On-chip self-awareness using Cyberphysical-Systems-on-Chip (CPSoC).
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

2013
Adaptive Technique for Computationally Efficient Time Delay and Magnitude Estimation of Sinusoidal Signals.
CoRR, 2013

2012
Cross-layer virtual observers for embedded multiprocessor system-on-chip (MPSoC).
Proceedings of the 11th Workshop on Adaptive and Reflective Middleware, 2012

2011
A hardware-software co-design approach to a JPEG encoder design for a planetary micro-rover application.
Proceedings of the Intelligent Robots and Computer Vision XXVIII: Algorithms and Techniques, 2011

2008
Software-Based Resolver-to-Digital Conversion Using a DSP.
IEEE Trans. Ind. Electron., 2008


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