Abbas BanaiyanMofrad

Affiliations:
  • University of California, Irvine, USA


According to our database1, Abbas BanaiyanMofrad authored at least 21 papers between 2005 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
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PhD thesis 
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Online presence:

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Bibliography

2017
Redundancy-aware Design Space Exploration for Memory Reliability in Many-cores.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2017

2016
Cross-layer virtual/physical sensing and actuation for resilient heterogeneous many-core SoCs.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Resilient On-Chip Memory Design in the Nano Era.
PhD thesis, 2015

Using a Flexible Fault-Tolerant Cache to Improve Reliability for Ultra Low Voltage Operation.
ACM Trans. Embed. Comput. Syst., 2015

DPCS: Dynamic Power/Capacity Scaling for SRAM Caches in the Nanoscale Era.
ACM Trans. Archit. Code Optim., 2015

Exploiting Partially-Forgetful Memories for Approximate Computing.
IEEE Embed. Syst. Lett., 2015

Protecting caches against multi-bit errors using embedded erasure coding.
Proceedings of the 20th IEEE European Test Symposium, 2015

2014
NoC-based fault-tolerant cache design in chip multiprocessors.
ACM Trans. Embed. Comput. Syst., 2014

Power / Capacity Scaling: Energy Savings With Simple Fault-Tolerant Caches.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Multi-Layer Memory Resiliency.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Defuzzification block: New algorithms, and efficient hardware and software implementation issues.
Eng. Appl. Artif. Intell., 2013

REMEDIATE: A scalable fault-tolerant architecture for low-power NUCA cache in tiled CMPs.
Proceedings of the International Green Computing Conference, 2013

Modeling and analysis of fault-tolerant distributed memories for networks-on-chip.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Reliable On-Chip Memory Design for CMPs.
Proceedings of the IEEE 31st Symposium on Reliable Distributed Systems, 2012

A novel NoC-based design for fault-tolerance of last-level caches in CMPs.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011
FFT-cache: a flexible fault-tolerant cache architecture for ultra low voltage operation.
Proceedings of the 14th International Conference on Compilers, 2011

2008
Design of a Custom Packet Switching Engine for Network Applications.
Proceedings of the Advances in Computer Science and Engineering, 2008

2006
Hardware implementation and comparison of new defuzzification techniques in fuzzy processors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Software Implementation Issues of Existing and New Defuzzification Methods.
Proceedings of the IEEE International Conference on Fuzzy Systems, 2006

A concurrent testing method for NoC switches.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Cost-Performance Co-Analysis in VLSI Implementation of Existing and New Defuzzification Methods.
Proceedings of the 2005 International Conference on Computational Intelligence for Modelling Control and Automation (CIMCA 2005), 2005


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