Amitava Majumdar

According to our database, Amitava Majumdar authored at least 33 papers between 1988 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2019

Innovative Design for Test in State-of-the-Art Analog Systems.

Hans Martin von Staudt, Amit Majumdar, Bill Taylor, Jennifer Kitchen

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

2018

Concurrent Sampling with Local Digitization - An Alternative to Analog Test Bus.

Nanqi Liu, Shravan K. Chaganti, Zhiqiang Liu, Degang Chen, Amitava Majumdar

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Handling Clock-Domain Crossings in Dual Clock-Edge Logic for DFx Features.

Amitava Majumdar, Balakrishna Jayadev

Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017

Foreword.

Yiorgos Makris, Srivaths Ravi, Amit Majumdar

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

A digital clock-less pulse stretcher with application in deep sub-nanosecond pulse detection.

Zhiqiang Liu, Nanqi Liu, Shravan K. Chaganti, Degang Chen, Amitava Majumdar

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Field profiling & monitoring of payload transistors in FPGAs.

Da Cheng, Amitava Majumdar, Xiaobao Wang, Nui Chong

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Architecture for Reliable Scan-Dump in the Presence of Multiple Asynchronous Clock Domains in FPGA SoCs.

Amitava Majumdar, Balakrishna Jayadev, Da Cheng, Albert Lin

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

Special panel session IIB: "System validation and silicon debug - Is standardization possible?".

Mike Ricchetti, Eric Rentschler, Amit Majumdar, Mike Lowe, Mark LaVine, Skip Lindsey, Sharad Kumar

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Application debug in FPGAs in the presence of multiple asynchronous clocks.

Georgios Tzimpragos, Da Cheng, Stephanie Tapp, Balakrishna Jayadev, Amitava Majumdar

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

2014

Hot topic session 9C: Test and fault tolerance for emerging memory technologies.

Suriya Natarajan, Amitava Majumdar, Jeyavijayan Rajendran

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Innovative practices session 4C: Disruptive solutions in the non-digital world.

Amitava Majumdar, Suriya Natarajan, Stephen K. Sunter, Prashant Goteti, Ke Huang

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Innovative practices session 3C: Solving today's test challenges.

John Kim, Wolfgang Meyer, T. M. Mak, Amitava Majumdar

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Avoiding burnt probe tips: Practical solutions for testing internally regulated power supplies.

Richard Swanson, Anna Wong, Suraj Ethirajan, Amitava Majumdar

Proceedings of the 19th IEEE European Test Symposium, 2014

2012

Power Characterization of Embedded SRAMs for Power Binning.

Yang Zhao, Lisa Grenier, Amitava Majumdar

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

2011

Special session 5B: Panel How much toggle activity should we be testing with?

Xiaoqing Wen, Mohammad Tehranipoor, Rohit Kapur, Anand Bhat, Amitava Majumdar, LeRoy Winemberg

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

A Novel mechanism for speed characterization during delay test.

Amitava Majumdar, Arani Sinha, Nehal Patel, Ramamurthy Setty, Yan Dong, Shu-Hsuan Chou

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

2009

Panel: Analog Characterization and Test: The Long Road to Realization.

Arani Sinha, Amitava Majumdar, Vasu Ganti

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

2006

Hold time validation on silicon and the relevance of hazards in timing analysis.

Amitava Majumdar, Wei-Yu Chen, Jun Guo

Proceedings of the 43rd Design Automation Conference, 2006

2003

Instruction Based BIST for Board/System Level Test of External Memories and Internconnects.

Olivier Caty, Ismet Bayraktaroglu, Amitava Majumdar, Richard Lee, John Bell, Lisa Curhan

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002

A Scalable, Low Cost Design-for-Test Architecture for UltraSPARC^TM Chip Multi-Processors.

Ishwar Parulkar, Thomas A. Ziaja, Rajesh Pendurkar, Anand D'Souza, Amitava Majumdar

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001

Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors.

Kamran Zarrineh, Thomas A. Ziaja, Amitava Majumdar

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

2000

Test-set partitioning for multi-weighted random LFSRs.

Dimitri Kagaris, Spyros Tragoudas, Amitava Majumdar

Integr., 2000

1998

Ground Bounce Considerations in DC Parametric Test Generation Using Boundary Scan.

Amitava Majumdar, Michio Komoda, Tim Ayres

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

On-Chip Test Embedding for Multi-Weighted Random LFSRs.

Dimitrios Kagaris, Spyros Tragoudas, Amitava Majumdar

Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

1996

On the Use of Counters for Reproducing Deterministic Test Sets.

Dimitrios Kagaris, Spyros Tragoudas, Amitava Majumdar

IEEE Trans. Computers, 1996

Deterministic Test Pattern Reproduction by a Counter.

Dimitrios Kagaris, Spyros Tragoudas, Amitava Majumdar

Proceedings of the 1996 European Design and Test Conference, 1996

1993

Probabilistic characterization of controllability in general homogeneous circuits.

Amitava Majumdar, Sarma Sastry

Comput. Aided Des., 1993

Statistical Analysis of Controllability.

Amitava Majumdar, Sarma Sastry

Proceedings of the Sixth International Conference on VLSI Design, 1993

1992

On the Distribution of Fault Coverage and Test length in Random Testing of Combinational Circuits.

Amitava Majumdar, Sarma Sastry

Proceedings of the 29th Design Automation Conference, 1992

1991

Test efficiency analysis of random self-test of sequential circuits.

Sarma Sastry, Amitava Majumdar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

A Branching Process Model for Observability Analysis of Combinational Circuits.

Sarma Sastry, Amitava Majumdar

Proceedings of the 28th Design Automation Conference, 1991

1990

Fault Tolerance in Linear Systolic Arrays Using Time Redundancy.

Amitava Majumdar, Cauligi S. Raghavendra, Melvin A. Breuer

IEEE Trans. Computers, 1990

1988

Fault tolerance and testing aspects of an architecture for a generalized sidelobe cancellor.

Melvin A. Breuer, Amitava Majumdar, Cauligi S. Raghavendra

Proceedings of the Computer Design: VLSI in Computers and Processors, 1988