Yoshimitsu Yanagawa

According to our database, Yoshimitsu Yanagawa authored at least 7 papers between 2003 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2013

On-chip base sequencing using a two-stage reaction-control scheme: 3.6-times-faster and 1/100-reduced-data-volume ISFET-based DNA sequencer.

Yoshimitsu Yanagawa, Naoshi Itabashi, Sonoko Migitaka, Takahide Yokoi, Makiko Yoshida, Takayuki Kawahara

Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013

2012

Fluctuation Tolerant Charge-Integration Read Scheme for Ultrafast DNA Sequencing with Nanopore Device.

Kazuo Ono, Yoshimitsu Yanagawa, Akira Kotabe, Riichiro Takemura, Tatsuo Nakagawa, Tomio Iwasaki, Takayuki Kawahara

IEICE Trans. Electron., 2012

Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays.

Akira Kotabe, Riichiro Takemura, Yoshimitsu Yanagawa, Tomonori Sekiguchi, Kiyoo Itoh

IEICE Trans. Electron., 2012

Fluctuation tolerant read scheme for ultrafast DNA sequencing with nanopore device.

Yoshimitsu Yanagawa, Kazuo Ono, Akira Kotabe, Riichiro Takemura, Tatsuo Nakagawa, Tomio Iwasaki, Takayuki Kawahara

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing.

Tomonori Sekiguchi, Kazuo Ono, Akira Kotabe, Yoshimitsu Yanagawa

IEEE J. Solid State Circuits, 2011

2010

0.5-V Low- V _T CMOS Preamplifier for Low-Power and High-Speed Gigabit-DRAM Arrays.

Akira Kotabe, Yoshimitsu Yanagawa, Satoru Akiyama, Tomonori Sekiguchi

IEEE J. Solid State Circuits, 2010

2003

Complexity Analysis of a Cache Controller for Speculative Multithreading Chip Multiprocessors.

Yoshimitsu Yanagawa, Luong Dinh Hung, Chitaka Iwama, Niko Demus Barli, Shuichi Sakai, Hidehiko Tanaka

Proceedings of the High Performance Computing - HiPC 2003, 10th International Conference, 2003