Satoru Takase

According to our database, Satoru Takase authored at least 3 papers between 1999 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

A 130.7-mm² 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology.

Tz-Yi Liu, Tian Hong Yan, Roy Scheuerlein, Yingchang Chen, Jeffrey KoonYee Lee, Gopinath Balakrishnan, Gordon Yee, Henry Zhang, Alex Yap, Jingwen Ouyang, Takahiko Sasaki, Ali Al-Shamma, Chin-Yu Chen, Mayank Gupta, Greg Hilton, Achal Kathuria, Vincent Lai, Masahide Matsumoto, Anurag Nigam, Anil Pai, Jayesh Pakhale, Chang Hua Siau, Xiaoxia Wu, Yibo Yin, Nicolas Nagel, Yoichiro Tanaka, Masaaki Higashitani, Tim Minvielle, Chandu Gorla, Takayuki Tsukamoto, Takeshi Yamaguchi, Mutsumi Okajima, Takayuki Okamura, Satoru Takase, Hirofumi Inoue, Luca Fasoli

IEEE J. Solid State Circuits, 2014

2013

A 130.7mm² 2-layer 32Gb ReRAM memory device in 24nm technology.

Tz-Yi Liu, Tian Hong Yan, Roy Scheuerlein, Yingchang Chen, Jeffrey KoonYee Lee, Gopinath Balakrishnan, Gordon Yee, Henry Zhang, Alex Yap, Jingwen Ouyang, Takahiko Sasaki, Sravanti Addepalli, Ali Al-Shamma, Chin-Yu Chen, Mayank Gupta, Greg Hilton, Saurabh Joshi, Achal Kathuria, Vincent Lai, Deep Masiwal, Masahide Matsumoto, Anurag Nigam, Anil Pai, Jayesh Pakhale, Chang Hua Siau, Xiaoxia Wu, Ronald Yin, Liping Peng, Jang Yong Kang, Sharon Huynh, Huijuan Wang, Nicolas Nagel, Yoichiro Tanaka, Masaaki Higashitani, Tim Minvielle, Chandu Gorla, Takayuki Tsukamoto, Takeshi Yamaguchi, Mutsumi Okajima, Takayuki Okamura, Satoru Takase, Takahiko Hara, Hirofumi Inoue, Luca Fasoli, Mehrdad Mofidi, Ritu Shrivastava, Khandker Quader

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

1999

A 1.6-GByte/s DRAM with flexible mapping redundancy technique and additional refresh scheme.

Satoru Takase, Natsuki Kushiyama

IEEE J. Solid State Circuits, 1999