Takahiko Sasaki

According to our database1, Takahiko Sasaki authored at least 7 papers between 2008 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2014
A 130.7-mm<sup>2</sup> 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology.
IEEE J. Solid State Circuits, 2014

2013

2010
A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm<sup>2</sup> cell in 32nm high-k metal-gate CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
A 0.7 V Single-Supply SRAM With 0.495 µm<sup>2</sup> Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme.
IEEE J. Solid State Circuits, 2009

A process-variation-tolerant dual-power-supply SRAM with 0.179µm<sup>2</sup> Cell in 40nm CMOS using level-programmable wordline driver.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
Direct Cell-Stability Test Techniques for an SRAM Macro with Asymmetric Cell-Bias-Voltage Modulation.
Proceedings of the 2008 IEEE International Test Conference, 2008

A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-×-ratio Memory Cell.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008


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