Jang Yong Kang

According to our database, Jang Yong Kang authored at least 3 papers between 2012 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology.

Chang Hua Siau, Kwang-Ho Kim, Seungpil Lee, Katsuaki Isobe, Noboru Shibata, Kapil Verma, Takuya Ariki, Jason Li, Jong Yuh, Anirudh Amarnath, Qui Nguyen, Ohwon Kwon, Stanley Jeong, Heguang Li, Hua-Ling Hsu, Taiyuan Tseng, Steve Choi, Siddhesh Darne, Pradeep Anantula, Alex Yap, Hardwell Chibvongodze, Hitoshi Miwa, Minoru Yamashita, Mitsuyuki Watanabe, Koichiro Hayashi, Yosuke Kato, Toru Miwa, Jang Yong Kang, Masatoshi Okumura, Naoki Ookuma, Muralikrishna Balaga, Venky Ramachandra, Aki Matsuda, Swaroop Kulkarni, Raghavendra Rachineni, Pai K. Manjunath, Masahito Takehara, Anil Pai, Srinivas Rajendra, Toshiki Hisada, Ryo Fukuda, Naoya Tokiwa, Kazuaki Kawaguchi, Masashi Yamaoka, Hiromitsu Komai, Takatoshi Minamoto, Masaki Unno, Susumu Ozawa, Hiroshi Nakamura, Tomoo Hishida, Yasuyuki Kajitani, Lei Lin

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2013

A 130.7mm² 2-layer 32Gb ReRAM memory device in 24nm technology.

Tz-Yi Liu, Tian Hong Yan, Roy Scheuerlein, Yingchang Chen, Jeffrey KoonYee Lee, Gopinath Balakrishnan, Gordon Yee, Henry Zhang, Alex Yap, Jingwen Ouyang, Takahiko Sasaki, Sravanti Addepalli, Ali Al-Shamma, Chin-Yu Chen, Mayank Gupta, Greg Hilton, Saurabh Joshi, Achal Kathuria, Vincent Lai, Deep Masiwal, Masahide Matsumoto, Anurag Nigam, Anil Pai, Jayesh Pakhale, Chang Hua Siau, Xiaoxia Wu, Ronald Yin, Liping Peng, Jang Yong Kang, Sharon Huynh, Huijuan Wang, Nicolas Nagel, Yoichiro Tanaka, Masaaki Higashitani, Tim Minvielle, Chandu Gorla, Takayuki Tsukamoto, Takeshi Yamaguchi, Mutsumi Okajima, Takayuki Okamura, Satoru Takase, Takahiko Hara, Hirofumi Inoue, Luca Fasoli, Mehrdad Mofidi, Ritu Shrivastava, Khandker Quader

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

128Gb 3b/cell NAND flash memory in 19nm technology with 18MB/s write rate and 400Mb/s toggle mode.

Yan Li, Seungpil Lee, Ken Oowada, Hao Nguyen, Qui Nguyen, Nima Mokhlesi, Cynthia Hsu, Jason Li, Venky Ramachandra, Teruhiko Kamei, Masaaki Higashitani, Tuan Pham, Mitsuaki Honma, Yoshihisa Watanabe, Kazumi Ino, Binh Le, Byungki Woo, Khin Htoo, Taiyuan Tseng, Long Pham, Frank Tsai, Kwang-Ho Kim, Yi-Chieh Chen, Min She, Jonghak Yuh, Alex Chu, Chen Chen, Ruchi Puri, Hung-Szu Lin, Yi-Fang Chen, William Mak, Jonathan Huynh, Jim Chan, Mitsuyuki Watanabe, Daniel Yang, Grishma Shah, Pavithra Souriraj, Dinesh Tadepalli, Tenugu Suman, Ray Gao, Viski Popuri, Behdad Azarbayjani, Ravindra Madpur, James Lan, Emilio Yero, Feng Pan, Patrick Hong, Jang Yong Kang, Farookh Moogat, Yupin Fong, Raul Cernea, Sharon Huynh, Cuong Trinh, Mehrdad Mofidi, Ritu Shrivastava, Khandker Quader

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012