Xiaoxia Wu

According to our database1, Xiaoxia Wu authored at least 36 papers between 2006 and 2020.

Collaborative distances:



In proceedings 
PhD thesis 


On csauthors.net:


Linear Convergence of Adaptive Stochastic Gradient Descent.
Proceedings of the 23rd International Conference on Artificial Intelligence and Statistics, 2020

Choosing the Sample with Lowest Loss makes SGD Robust.
Proceedings of the 23rd International Conference on Artificial Intelligence and Statistics, 2020

Implicit Regularization of Normalization Methods.
CoRR, 2019

Global Convergence of Adaptive Gradient Methods for An Over-parameterized Neural Network.
CoRR, 2019

On structural properties of <i>ABC</i>-minimal chemical trees.
Appl. Math. Comput., 2019

AdaGrad stepsizes: sharp convergence over nonconvex landscapes.
Proceedings of the 36th International Conference on Machine Learning, 2019

Methionine-Capped Gold Nanoclusters as a Fluorescence-Enhanced Probe for Cadmium(II) Sensing.
Sensors, 2018

AdaGrad stepsizes: Sharp convergence over nonconvex landscapes, from any initialization.
CoRR, 2018

WNGrad: Learn the Learning Rate in Gradient Descent.
CoRR, 2018

Spanning trees and recurrent configurations of a graph.
Appl. Math. Comput., 2017

Interoperation of layer-2/3 modular switches with 8QAM/16QAM integrated coherent optics over 2000 km open line system.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2017

A 130.7-mm<sup>2</sup> 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology.
IEEE J. Solid State Circuits, 2014

Height Probabilities in the Abelian Sandpile Model on the Generalized Trees.
Ars Comb., 2014


Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Estimating the Proportion of True Null Hypotheses in Nonparametric Exponential Mixture Model with Appication to the Leukemia Gene Expression Data.
Commun. Stat. Simul. Comput., 2012

Small Randic Index Ordering of Trees with k Pendant Vertices.
Ars Comb., 2012

Variation-Aware Task and Communication Mapping for MPSoC Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation.
IET Comput. Digit. Tech., 2011

Optical logic elementary circuits.
IET Circuits Devices Syst., 2011

Design exploration of hybrid caches with disparate memory technologies.
ACM Trans. Archit. Code Optim., 2010

Test-access mechanism optimization for core-based three-dimensional SOCs.
Microelectron. J., 2010

Cost-driven 3D integration with interconnect layers.
Proceedings of the 47th Design Automation Conference, 2010

Scan-chain design and optimization for three-dimensional integrated circuits.
ACM J. Emerg. Technol. Comput. Syst., 2009

Exploration of 3D stacked L2 cache design for high performance and efficient thermal control.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Hybrid cache architecture with disparate memory technologies.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Power and performance of read-write aware Hybrid Caches with non-volatile memories.
Proceedings of the Design, Automation and Test in Europe, 2009

Test-Access Solutions for Three-Dimensional SOCs.
Proceedings of the 2008 IEEE International Test Conference, 2008

Comparative analysis of NBTI effects on low power and high performance flip-flops.
Proceedings of the 26th International Conference on Computer Design, 2008

Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement.
Proceedings of the 45th Design Automation Conference, 2008

Variability-driven module selection with joint design time optimization and post-silicon tuning.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

On-chip bus thermal analysis and optimisation.
IET Comput. Digit. Tech., 2007

Scan chain design for three-dimensional integrated circuits (3D ICs).
Proceedings of the 25th International Conference on Computer Design, 2007

Variation-aware task allocation and scheduling for MPSoC.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Analysis of Subthreshold Finfet Circuits for Ultra-Low Power Design.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Guaranteeing performance yield in high-level synthesis.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006