Xiaoxia Wu

According to our database1, Xiaoxia Wu authored at least 62 papers between 2006 and 2024.

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Bibliography

2024
FP6-LLM: Efficiently Serving Large Language Models Through FP6-Centric Algorithm-System Co-Design.
CoRR, 2024

Exploring Post-training Quantization in LLMs from Comprehensive Study to Low Rank Compensation.
Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024

DeepSpeed Data Efficiency: Improving Deep Learning Model Quality and Training Efficiency via Efficient Data Sampling and Routing.
Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024

2023
A novel bias-alleviated hybrid ensemble model based on over-sampling and post-processing for fair classification.
Connect. Sci., December, 2023

ZeroQuant(4+2): Redefining LLMs Quantization with a New FP6-Centric Strategy for Diverse Generative Tasks.
CoRR, 2023

ZeroQuant-HERO: Hardware-Enhanced Robust Optimized Post-Training Quantization Framework for W8A8 Transformers.
CoRR, 2023

DeepSpeed4Science Initiative: Enabling Large-Scale Scientific Discovery through Sophisticated AI System Technologies.
CoRR, 2023

DeepSpeed-VisualChat: Multi-Round Multi-Image Interleave Chat via Multi-Modal Causal Attention.
CoRR, 2023

RenAIssance: A Survey into AI Text-to-Image Generation in the Era of Large Model.
CoRR, 2023

DeepSpeed-Chat: Easy, Fast and Affordable RLHF Training of ChatGPT-like Models at All Scales.
CoRR, 2023

ZeroQuant-FP: A Leap Forward in LLMs Post-Training W4A8 Quantization Using Floating-Point Formats.
CoRR, 2023

A Comprehensive Study on Post-Training Quantization for Large Language Models.
CoRR, 2023

Understanding INT4 Quantization for Transformer Models: Latency Speedup, Composability, and Failure Cases.
CoRR, 2023

Understanding Int4 Quantization for Language Models: Latency Speedup, Composability, and Failure Cases.
Proceedings of the International Conference on Machine Learning, 2023

2022
DeepSpeed Data Efficiency: Improving Deep Learning Model Quality and Training Efficiency via Efficient Data Sampling and Routing.
CoRR, 2022

Random-LTD: Random and Layerwise Token Dropping Brings Efficient Training for Large-scale Transformers.
CoRR, 2022

Extreme Compression for Pre-trained Transformers Made Simple and Efficient.
CoRR, 2022

ZeroQuant: Efficient and Affordable Post-Training Quantization for Large-Scale Transformers.
Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022

XTC: Extreme Compression for Pre-trained Transformers Made Simple and Efficient.
Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022

AdaLoss: A Computationally-Efficient and Provably Convergent Adaptive Gradient Method.
Proceedings of the Thirty-Sixth AAAI Conference on Artificial Intelligence, 2022

2021
Adaptive Differentially Private Empirical Risk Minimization.
CoRR, 2021

Hierarchical Learning for Generation with Long Source Sequences.
CoRR, 2021

When Do Curricula Work?
Proceedings of the 9th International Conference on Learning Representations, 2021

2020
Implicit Regularization and Convergence for Weight Normalization.
Proceedings of the Advances in Neural Information Processing Systems 33: Annual Conference on Neural Information Processing Systems 2020, 2020

Linear Convergence of Adaptive Stochastic Gradient Descent.
Proceedings of the 23rd International Conference on Artificial Intelligence and Statistics, 2020

Choosing the Sample with Lowest Loss makes SGD Robust.
Proceedings of the 23rd International Conference on Artificial Intelligence and Statistics, 2020

2019
Implicit Regularization of Normalization Methods.
CoRR, 2019

Global Convergence of Adaptive Gradient Methods for An Over-parameterized Neural Network.
CoRR, 2019

On structural properties of <i>ABC</i>-minimal chemical trees.
Appl. Math. Comput., 2019

AdaGrad stepsizes: sharp convergence over nonconvex landscapes.
Proceedings of the 36th International Conference on Machine Learning, 2019

Research on the Development Trend and Coping Strategies of Internet Finance.
Proceedings of the Cyber Security Intelligence and Analytics, 2019

2018
Methionine-Capped Gold Nanoclusters as a Fluorescence-Enhanced Probe for Cadmium(II) Sensing.
Sensors, 2018

Toward Transport Ecosystem Interoperability Enabled by Vendor-Diverse Coherent Optical Sources Over an Open Line System.
JOCN, 2018

AdaGrad stepsizes: Sharp convergence over nonconvex landscapes, from any initialization.
CoRR, 2018

WNGrad: Learn the Learning Rate in Gradient Descent.
CoRR, 2018

2017
Spanning trees and recurrent configurations of a graph.
Appl. Math. Comput., 2017

Interoperation of layer-2/3 modular switches with 8QAM/16QAM integrated coherent optics over 2000 km open line system.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2017

2014
A 130.7-mm<sup>2</sup> 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology.
IEEE J. Solid State Circuits, 2014

Height Probabilities in the Abelian Sandpile Model on the Generalized Trees.
Ars Comb., 2014

2013

2012
Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Estimating the Proportion of True Null Hypotheses in Nonparametric Exponential Mixture Model with Appication to the Leukemia Gene Expression Data.
Commun. Stat. Simul. Comput., 2012

Small Randic Index Ordering of Trees with k Pendant Vertices.
Ars Comb., 2012

2011
Variation-Aware Task and Communication Mapping for MPSoC Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation.
IET Comput. Digit. Tech., 2011

Optical logic elementary circuits.
IET Circuits Devices Syst., 2011

2010
Design exploration of hybrid caches with disparate memory technologies.
ACM Trans. Archit. Code Optim., 2010

Test-access mechanism optimization for core-based three-dimensional SOCs.
Microelectron. J., 2010

Cost-driven 3D integration with interconnect layers.
Proceedings of the 47th Design Automation Conference, 2010

2009
Scan-chain design and optimization for three-dimensional integrated circuits.
ACM J. Emerg. Technol. Comput. Syst., 2009

Exploration of 3D stacked L2 cache design for high performance and efficient thermal control.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Hybrid cache architecture with disparate memory technologies.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Power and performance of read-write aware Hybrid Caches with non-volatile memories.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Test-Access Solutions for Three-Dimensional SOCs.
Proceedings of the 2008 IEEE International Test Conference, 2008

Comparative analysis of NBTI effects on low power and high performance flip-flops.
Proceedings of the 26th International Conference on Computer Design, 2008

Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement.
Proceedings of the 45th Design Automation Conference, 2008

Variability-driven module selection with joint design time optimization and post-silicon tuning.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
On-chip bus thermal analysis and optimisation.
IET Comput. Digit. Tech., 2007

Scan chain design for three-dimensional integrated circuits (3D ICs).
Proceedings of the 25th International Conference on Computer Design, 2007

Variation-aware task allocation and scheduling for MPSoC.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006
Analysis of Subthreshold Finfet Circuits for Ultra-Low Power Design.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Guaranteeing performance yield in high-level synthesis.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006


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