Sean Atsatt

According to our database, Sean Atsatt authored at least 4 papers between 2014 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2017

3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration.

David Greenhill, Ron Ho, David M. Lewis, Herman Schmit, Kok Hong Chan, Andy Tong, Sean Atsatt, Dana How, Peter McElheny, Keith Duwel, Jeffrey Schulz, Darren Faulkner, Gopal Iyer, George Chen, Hee Kong Phoon, Han Wooi Lim, Wei-Yee Koay, Ty Garibay

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

Sectors: Divide & Conquer and Softwarization in the Design and Validation of the Stratix® 10 FPGA.

Dana L. How, Sean Atsatt

Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

2015

Arria™ 10 device architecture.

Jeffrey Tyhach, Mike Hutton, Sean Atsatt, Arifur Rahman, Brad Vest, David M. Lewis, Martin Langhammer, Sergey Y. Shumarayev, Tim Hoang, Allen Chan, Dong-Myung Choi, Dan Oh, Hae-Chang Lee, Jack Chui, Ket Chiew Sia, Edwin Kok, Wei-Yee Koay, Boon-Jin Ang

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

Design of a high-density SoC FPGA at 20nm.

Brad Vest, Sean Atsatt, Mike Hutton

Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014