David M. Lewis

According to our database1, David M. Lewis authored at least 41 papers between 1985 and 2017.

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Bibliography

2017
3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
The Stratix™ 10 Highly Pipelined FPGA Architecture.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Stratix™ 10 High Performance Routable Clock Networks.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2015

2013
Architectural enhancements in Stratix V™.
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

2011
An Empirical Evaluation of Similarity Coefficients for Binary Valued Data.
IJDWM, 2011

2010
A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

2009
Architectural enhancements in Stratix-IIITM and Stratix-IVTM.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

2005

2004
Improving FPGA Performance and Area Using an Adaptive Logic Module.
Proceedings of the Field Programmable Logic and Application, 2004

MAX II: A low-cost, high-performance LUT-based CPLD.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
The StratixTM routing and logic architecture.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

2002
Synthesizing datapath circuits for FPGAs with emphasis on area minimization.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Analytical Framework for Switch Block Design.
Proceedings of the Field-Programmable Logic and Applications, 2002

Circuit design of routing switches.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002

2001
Using sparse crossbars within LUT.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2001

2000
Generating highly-routable sparse crossbars for PLDs.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

Design of a VLIW Compute Accelerator on the Transmogrifier-2.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

1999
Procedural Texture Mapping on FPGAs.
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

1998
The Transmogrifier-2: a 1 million gate rapid-prototyping system.
IEEE Trans. VLSI Syst., 1998

1997
The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System.
Proceedings of the 1997 ACM/SIGDA Fifth International Symposium on Field Programmable Gate Arrays, 1997

Automated field-programmable compute accelerator design using partial evaluation.
Proceedings of the 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 1997

1996
Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays.
Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, 1996

1994
Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit.
IEEE Trans. Computers, 1994

Routing Architectures for Hierarchical Field Programmable Gate Arrays.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1993
A multiple-strength multiple-delay compiled-code logic simulator.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

Highly Selective "Analog" Filters Using Delta Sigma Based IIR Filtering.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

A Field Programmable Accelerator for Compiled-Code Applications.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

An accurate LNS arithmetic unit using interleaved memory function interpolator.
Proceedings of the 11th Symposium on Computer Arithmetic, 29 June, 1993

1992
A compiled-code hardware accelerator for circuit simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992

1991
A hierarchical compiled code event-driven logic simulator.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1991

Hector: A Hierarchically Structured Shared-memory Multiprocessor.
IEEE Computer, 1991

1990
Device model approximation using 2N trees.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1990

An Architecture for Addition and Subtraction of Long Word Length Numbers in the Logarithmic Number System.
IEEE Trans. Computers, 1990

Using Deducibility in Secure Network Modelling.
Proceedings of the ESORICS 90, 1990

1989
Hierarchical compiled event-driven logic simulation.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Algorithm design for a 30-bit integrated logarithmic processor.
Proceedings of the 9th Symposium on Computer Arithmetic, 1989

1988
Hardware accelerators for timing simulation of VLSI digital circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1988

A Programmable Hardware Accelerator for Compiled Electrical Simulation.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1986
Swamp: A Fast Processor for Smalltalk-80.
Proceedings of the Conference on Object-Oriented Programming Systems, 1986

1985
A hardware engine for analogue mode simulation of MOS digital circuits.
Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985


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