Ron Ho

According to our database1, Ron Ho authored at least 38 papers between 1998 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2017
3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
Scalable High-Radix Modular Crossbar Switches.
Proceedings of the 24th IEEE Annual Symposium on High-Performance Interconnects, 2016

2015
Modeling and Design of High-Radix On-Chip Crossbar Switches.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

High-efficiency crossbar switches using capacitively coupled signaling.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

2013
A 100+ Meter 12 Gb/s/Lane Copper Cable Link Based on Clock-Forwarding.
IEEE J. Solid State Circuits, 2013

Efficient techniques for canceling transceiver noise.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

A 33mW 100Gbps CMOS silicon photonic WDM transmitter using off-chip laser sources.
Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013

2012
10-Gbps, 5.3-mW Optical Transmitter and Receiver Circuits in 40-nm CMOS.
IEEE J. Solid State Circuits, 2012

A 100+ meter 12Gb/s/lane copper cable link based on clock-forwarding.
Proceedings of the Symposium on VLSI Circuits, 2012

A micro-architectural analysis of switched photonic multi-chip interconnects.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

2011
Energy-Efficient Error Control for Tightly Coupled Systems Using Silicon Photonic Interconnects.
JOCN, 2011

A 4.6GHz MDLL with -46dBc reference spur and aperture position tuning.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Digitally-assisted analog circuits for a 10 Gbps, 395 fJ/b optical receiver in 40 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
Guest Editorial for Special Issue on High-Performance Multichip Interconnections.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Optical Interconnect for High-End Computer Systems.
IEEE Des. Test Comput., 2010

High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Silicon-photonic network architectures for scalable, power-efficient multi-chip systems.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

Optical Interconnects in the Data Center.
Proceedings of the IEEE 18th Annual Symposium on High Performance Interconnects, 2010

Clocking Links in Multi-chip Packages: A Case Study.
Proceedings of the IEEE 18th Annual Symposium on High Performance Interconnects, 2010

2009
Computer Systems Based on Silicon Photonic Interconnects.
Proc. IEEE, 2009

Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2009

2008
High Speed and Low Energy Capacitively Driven On-Chip Wires.
IEEE J. Solid State Circuits, 2008

Transistor Variability in Nanometer-Scale Technologies (Forum).
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Optical Interconnects for Present and Future High-Performance Computing Systems.
Proceedings of the 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 2008

2007
Research Challenges for On-Chip Interconnection Networks.
IEEE Micro, 2007

Circuit Techniques to Enable 430Gb/s/mm2 Proximity Communication.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

On-chip samplers for test and debug of asynchronous circuits.
Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 2007

Robust Energy-Efficient Adder Topologies.
Proceedings of the 18th IEEE Symposium on Computer Arithmetic (ARITH-18 2007), 2007

2005
Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-μm CMOS.
IEEE J. Solid State Circuits, 2005

High-performance ULSI: the real limiter to interconnect scaling.
Proceedings of the Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), 2005

Challenges in Building a Flat-Bandwidth Memory Hierarchy for a Large-Scale Computer with Proximity Communication.
Proceedings of the 13th Annual IEEE Symposium on High Performance Interconnects (HOTIC 2005), 2005

2004
Proximity communication.
IEEE J. Solid State Circuits, 2004

Long Wires and Asynchronous Control.
Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004

An Adaptive OpenMP Loop Scheduler for Hyperthreaded SMPs.
Proceedings of the ISCA 17th International Conference on Parallel and Distributed Computing Systems, 2004

2001
The future of wires.
Proc. IEEE, 2001

2000
Smart Memories: a modular reconfigurable architecture.
Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000

1999
Interconnect scaling implications for CAD.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1998
Low-power SRAM design using half-swing pulse-mode techniques.
IEEE J. Solid State Circuits, 1998


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