Muhammet Mustafa Ozdal

Özcan Özturk

ACM Trans. Embed. Comput. Syst., March, 2023

Load balanced locality-aware parallel SGD on multicore architectures for latent factor based collaborative filtering.

[BibT_eX]

[DOI]

Selcuk Gulcan

Cevdet Aykanat

Future Gener. Comput. Syst., 2023

2022

Learning to Collide: Recommendation System Model Compression with Learned Hash Functions.

[BibT_eX]

[DOI]

Benjamin Ghaemmaghami

CoRR, 2022

Understanding data storage and ingestion for large-scale deep recommendation model training: industrial product.

[BibT_eX]

[DOI]

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

Software-hardware co-design for fast and scalable training of deep learning recommendation models.

[BibT_eX]

[DOI]

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

2021

Understanding and Co-designing the Data Ingestion Pipeline for Industry-Scale RecSys Training.

[BibT_eX]

[DOI]

CoRR, 2021

High-performance, Distributed Training of Large-scale Deep Learning Recommendation Models.

[BibT_eX]

[DOI]

CoRR, 2021

2020

Deep Learning Training in Facebook Data Centers: Design of Scale-up and Scale-out Systems.

[BibT_eX]

[DOI]

CoRR, 2020

2019

Improving Efficiency of Parallel Vertex-Centric Algorithms for Irregular Graphs.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2019

Improving Programmability and Efficiency of Large-Scale Graph Analytics for FPGA Platforms.

[BibT_eX]

[DOI]

Proceedings of the 2019 International Symposium on Physical Design, 2019

2018

Introduction to the Special Section on Advances in Physical Design Automation.

[BibT_eX]

[DOI]

Chris Chu

Mustafa Ozdal

ACM Trans. Design Autom. Electr. Syst., 2018

A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators.

[BibT_eX]

[DOI]

Andrey Ayupov

Serif Yesil

Taemin Kim

Steven M. Burns

Ozcan Ozturk

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Guest Editors' Introduction: Hardware Accelerators for Data Centers.

[BibT_eX]

[DOI]

Mustafa Ozdal

Gi-Joon Nam

Debbie Marr

IEEE Des. Test, 2018

Emerging Accelerator Platforms for Data Centers.

[BibT_eX]

[DOI]

IEEE Des. Test, 2018

2017

Graph Analytics Accelerators for Cognitive Systems.

[BibT_eX]

[DOI]

IEEE Micro, 2017

2016

Energy Efficient Architecture for Graph Analytics Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

2015

A Novel Method for Scaling Iterative Solvers: Avoiding Latency Overhead of Parallel Sparse-Matrix Vector Multiplies.

[BibT_eX]

[DOI]

R. Oguz Selvitopi

Cevdet Aykanat

IEEE Trans. Parallel Distributed Syst., 2015

Wavelet-Based Trace Alignment Algorithms for Heterogeneous Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Guest Editorial: Special Section on Physical Design Techniques for Advanced Technology Nodes.

[BibT_eX]

[DOI]

Azadeh Davoodi

Jiang Hu

Cliff C. N. Sze

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Hardware Accelerator Design for Data Centers.

[BibT_eX]

[DOI]

Serif Yesil

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Architectural Requirements for Energy Efficient Execution of Graph Analytics Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014

Algorithms for Maze Routing With Exact Matching Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2013

An improved benchmark suite for the ISPD-2013 discrete cell sizing contest.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2013

Trace alignment algorithms for offline workload analysis of heterogeneous architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2012

Algorithms for Gate Sizing and Device Parameter Selection for High-Performance Designs.

[BibT_eX]

[DOI]

Steven M. Burns

Jiang Hu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

The ISPD-2012 discrete cell sizing contest and benchmark suite.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2012

Maze routing algorithms with exact matching constraints for analog and mixed signal designs.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011

An Algorithmic Study of Exact Route Matching for Integrated Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Gate sizing and device technology selection algorithms for high-performance industrial designs.

[BibT_eX]

[DOI]

Steven M. Burns

Jiang Hu

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2009

Archer: A History-Based Global Routing Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Detailed-Routing Algorithms for Dense Pin Clusters in Integrated Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Exact route matching algorithms for analog and mixed signal integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008

Global Routing Formulation and Maze Routing.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Optimal routing algorithms for rectilinear pin clusters in high-density multichip modules.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2008

Simultaneous Escape-Routing Algorithms for Via Minimization of High-Speed Boards.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

2007

Archer: a history-driven global routing algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Optimal bus sequencing for escape routing in dense PCBs.

[BibT_eX]

[DOI]

Hui Kong

Tan Yan

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Escape Routing For Dense Pin Clusters In Integrated Circuits.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

2006

Two-layer bus routing for high-speed printed circuit boards.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2006

A Length-Matching Routing Algorithm for High-Performance Printed Circuit Boards.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Algorithms for simultaneous escape routing and Layer assignment of dense PCBs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Algorithmic study of single-layer bus routing for high-speed boards.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

2005

Routing Algorithms for High-Performance VLSI Packaging

[BibT_eX]

[DOI]

PhD thesis, 2005

Optimal routing algorithms for pin clusters in high-density multichip modules.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

An escape routing framework for dense boards with high-speed design constraints.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

2004

Hypergraph Models and Algorithms for Data-Pattern-Based Clustering.

[BibT_eX]

[DOI]

Cevdet Aykanat

Data Min. Knowl. Discov., 2004

A Two-Layer Bus Routing Algorithm for High-Speed Boards.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

A provably good algorithm for high performance bus routing.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Simultaneous escape routing and layer assignment for dense PCBs.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2003

Length-Matching Routing for High-Speed Printed Circuit Boards.

[BibT_eX]

[DOI]