Muhammet Mustafa Ozdal

According to our database1, Muhammet Mustafa Ozdal authored at least 41 papers between 2003 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
Other 

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Bibliography

2019
Improving Efficiency of Parallel Vertex-Centric Algorithms for Irregular Graphs.
IEEE Trans. Parallel Distrib. Syst., 2019

Improving Programmability and Efficiency of Large-Scale Graph Analytics for FPGA Platforms.
Proceedings of the 2019 International Symposium on Physical Design, 2019

2018
Introduction to the Special Section on Advances in Physical Design Automation.
ACM Trans. Design Autom. Electr. Syst., 2018

A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Guest Editors' Introduction: Hardware Accelerators for Data Centers.
IEEE Design & Test, 2018

Emerging Accelerator Platforms for Data Centers.
IEEE Design & Test, 2018

2017
Graph Analytics Accelerators for Cognitive Systems.
IEEE Micro, 2017

2016
Energy Efficient Architecture for Graph Analytics Accelerators.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

2015
A Novel Method for Scaling Iterative Solvers: Avoiding Latency Overhead of Parallel Sparse-Matrix Vector Multiplies.
IEEE Trans. Parallel Distrib. Syst., 2015

Wavelet-Based Trace Alignment Algorithms for Heterogeneous Architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Guest Editorial: Special Section on Physical Design Techniques for Advanced Technology Nodes.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Hardware Accelerator Design for Data Centers.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Architectural Requirements for Energy Efficient Execution of Graph Analytics Applications.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014
Algorithms for Maze Routing With Exact Matching Constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

2013
An improved benchmark suite for the ISPD-2013 discrete cell sizing contest.
Proceedings of the International Symposium on Physical Design, 2013

Trace alignment algorithms for offline workload analysis of heterogeneous architectures.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2012
Algorithms for Gate Sizing and Device Parameter Selection for High-Performance Designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

The ISPD-2012 discrete cell sizing contest and benchmark suite.
Proceedings of the International Symposium on Physical Design, 2012

Maze routing algorithms with exact matching constraints for analog and mixed signal designs.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011
An Algorithmic Study of Exact Route Matching for Integrated Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Gate sizing and device technology selection algorithms for high-performance industrial designs.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2009
Archer: A History-Based Global Routing Algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Detailed-Routing Algorithms for Dense Pin Clusters in Integrated Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Exact route matching algorithms for analog and mixed signal integrated circuits.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008
Global Routing Formulation and Maze Routing.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Optimal routing algorithms for rectilinear pin clusters in high-density multichip modules.
ACM Trans. Design Autom. Electr. Syst., 2008

Simultaneous Escape-Routing Algorithms for Via Minimization of High-Speed Boards.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

2007
Archer: a history-driven global routing algorithm.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Optimal bus sequencing for escape routing in dense PCBs.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Escape Routing For Dense Pin Clusters In Integrated Circuits.
Proceedings of the 44th Design Automation Conference, 2007

2006
Two-layer bus routing for high-speed printed circuit boards.
ACM Trans. Design Autom. Electr. Syst., 2006

A Length-Matching Routing Algorithm for High-Performance Printed Circuit Boards.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Algorithms for simultaneous escape routing and Layer assignment of dense PCBs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Algorithmic study of single-layer bus routing for high-speed boards.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

2005
Optimal routing algorithms for pin clusters in high-density multichip modules.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

An escape routing framework for dense boards with high-speed design constraints.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

2004
Hypergraph Models and Algorithms for Data-Pattern-Based Clustering.
Data Min. Knowl. Discov., 2004

A Two-Layer Bus Routing Algorithm for High-Speed Boards.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

A provably good algorithm for high performance bus routing.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Simultaneous escape routing and layer assignment for dense PCBs.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2003
Length-Matching Routing for High-Speed Printed Circuit Boards.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003


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