S. Arash Mirhaj

According to our database1, S. Arash Mirhaj authored at least 5 papers between 2008 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2022
Automated Design of Analog Circuits Using Reinforcement Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2015
14.9 Sub-sampling all-digital fractional-N frequency synthesizer with -111dBc/Hz in-band phase noise and an FOM of -242dB.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2011
High speed sample and hold design using closed-loop pole-zero cancelation.
Microelectron. J., 2011

Linearity improvement of open-loop NMOS source-follower sample and hold circuits.
IET Circuits Devices Syst., 2011

2008
A Novel Low Power 1 GS/s S&H Architecture With Improved Analog Bandwidth.
IEEE Trans. Circuits Syst. II Express Briefs, 2008


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