Rajeev Jain

Orcid: 0000-0001-9014-2843

According to our database1, Rajeev Jain authored at least 52 papers between 1984 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 1999, "For contributions to computer-aided design tools for signal processing circuits.".

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2024
Less is More: Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits.
CoRR, 2024

2023
Framework and Methodology for Verification of a Complex Scientific Simulation Software, Flash-X.
CoRR, 2023

An Automation Framework for Comparison of Cancer Response Models Across Configurations.
Proceedings of the 19th IEEE International Conference on e-Science, 2023

2022
Automated Design of Analog Circuits Using Reinforcement Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Flash-X: A multiphysics simulation software instrument.
SoftwareX, 2022

Exascale models of stellar explosions: Quintessential multi-physics simulation.
Int. J. High Perform. Comput. Appl., 2022

From System-on-Chip (SoC) to System on Multi-Chip (SoMC) architectures: Scaling integrated systems beyond the limitations of deep-submicron single chip technologies.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Accelerating Flash-X Simulations with Asynchronous I/O.
Proceedings of the IEEE/ACM International Parallel Data Systems Workshop, 2022

2021
Checkpoint/Restart for Lagrangian particle mesh with AMR in community code FLASH-X.
CoRR, 2021

Fast and Accurate PPA Modeling with Transfer Learning.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

2020
Data-driven CAD or Algorithm-Driven CAD: Competitors or Collaborators?
Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020

2018
CANDLE/Supervisor: a workflow framework for machine learning applied to cancer research.
BMC Bioinform., 2018

Efficient reinforcement learning for automating human decision-making in SoC design.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Kano integrated robust design approach for aesthetical product design: a case study of a car profile.
J. Intell. Manuf., 2017

2014
Using data mining synergies for evaluating criteria at pre-qualification stage of supplier selection.
J. Intell. Manuf., 2014

A Kano model, AHP and M-TOPSIS method-based technique for disassembly line balancing under fuzzy environment.
Appl. Soft Comput., 2014

2013
A heuristic approach for U-shaped assembly line balancing to improve labor productivity.
Comput. Ind. Eng., 2013

PostBL: Post-mesh Boundary Layer Mesh Generation Tool.
Proceedings of the 22nd International Meshing Roundtable, 2013

2012
Creating geometry and mesh models for nuclear reactor core geometries using a lattice hierarchy-based approach.
Eng. Comput., 2012

A New Heuristic for Disassembly Line Balancing Problems with AND/OR Precedence Relations.
Proceedings of the Second International Conference on Soft Computing for Problem Solving, 2012

2009
Spectrum Sensing Design Framework Based on Cross-Layer Optimization of Detection Efficiency.
Proceedings of IEEE International Conference on Communications, 2009

1999
Adaptive radio for multimedia wireless links.
IEEE J. Sel. Areas Commun., 1999

DEFACTO: A Design Environment for Adaptive Computing Technology.
Proceedings of the Parallel and Distributed Processing, 1999

1998
A 110-K transistor 25-MPixels/s configurable image transform processor unit.
IEEE J. Solid State Circuits, 1998

Simulation and Synthesis of VLSI Communication Systems.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Panel: Challenges for Future Systems on a Chip.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

1997
On-line broadcast archives for interactive video.
IEEE Trans. Broadcast., 1997

1996
An integrated testbed for wireless multimedia computing.
J. VLSI Signal Process., 1996

VLSI in Mobile Communication.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

A low power architecture for wireless multimedia systems: lessons learned from building a power hog.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1995
Strategies for design automation of high speed digital filters.
J. VLSI Signal Process., 1995

Techniques for FPGA Implementation of Video Compression Systems.
Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

1994
A single-chip 12.7 Mchips/s digital IF BPSK direct sequence spread-spectrum transceiver in 1.2 μm CMOS.
IEEE J. Solid State Circuits, December, 1994

An Algorithm-Driven Processor Design for Video Compression.
Proceedings of the Proceedings 1994 International Conference on Image Processing, 1994

1993
Performance Analysis of an All-Digital BPSK Direct-Sequence Spread-Spectrum IF Receiver Architecture.
IEEE J. Sel. Areas Commun., 1993

An Integrated Technology CAD System for Process and Device Designers.
Proceedings of the Sixth International Conference on VLSI Design, 1993

1992
DDFSGEN.
J. VLSI Signal Process., 1992

An integrated circuit design for pruned tree-search vector quantization encoding with an off-chip controller.
IEEE Trans. Circuits Syst. Video Technol., 1992

Architectures and integrated circuits for real time vector quantization of images.
Proceedings of the 1992 IEEE International Conference on Acoustics, 1992

Decimation filter compiler for oversampling A/D applications.
Proceedings of the 1992 IEEE International Conference on Acoustics, 1992

Hi-PASS: a computer-aided synthesis system for maximally parallel digital signal processing ASICs.
Proceedings of the 1992 IEEE International Conference on Acoustics, 1992

Real Time Implementation of Pruned Tree Search Vector Quantization.
Proceedings of the IEEE Data Compression Conference, 1992

1991
FIRGEN: a computer-aided design system for high performance FIR filter integrated circuits.
IEEE Trans. Signal Process., 1991

An integrated CAD system for algorithm-specific IC design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Computer-aided design of high-speed lattice wave digital filter integrated circuits.
Proceedings of the 1991 International Conference on Acoustics, 1991

1990
A functional silicon compiler for high speed FIR digital filters.
Proceedings of the 1990 International Conference on Acoustics, 1990

1989
FDT-a design tool for switched capacitor filters.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988
Architectural strategies for an application-specific synchronous multiprocessor environment.
IEEE Trans. Acoust. Speech Signal Process., 1988

An ASIC architecture for contour line filtering.
Proceedings of the IEEE International Conference on Acoustics, 1988

1986
A fast adder-based multiplication unit for customised digital signal processors.
Proceedings of the IEEE International Conference on Acoustics, 1986

1985
CAD Tools for the optimized design of custom VLSI wave digital filters.
Proceedings of the IEEE International Conference on Acoustics, 1985

1984
Efficient CAD tools for the coefficient optimisation of arbitrary integrated digital filters.
Proceedings of the IEEE International Conference on Acoustics, 1984


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