Shawn S. H. Hsu

Orcid: 0000-0002-0910-7096

According to our database1, Shawn S. H. Hsu authored at least 18 papers between 2007 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Transmission Lines-Based Impedance Matching Technique for Broadband Rectifier.
IEEE Access, 2021

F5: Enabling New System Architectures with 2.5D, 3D, and Chiplets.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Session 13 Overview: Cryo-CMOS for Quantum Computing Technology Directions Subcommittee.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
High-Power Wire Bonded GaN Rectifier for Wireless Power Transmission.
IEEE Access, 2020

2018
A Transformer-Based Current-Reuse QVCO With an FoM Up to -200.5 dBc/Hz.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

2017
A Sierpinski Space-Filling Clock Tree Using Multiply-by-3 Fractal-Coupled Ring Oscillators.
IEEE J. Solid State Circuits, 2017

2015
A low phase-noise class-C VCO using novel 8-shaped transformer.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
A 10-Gb/s Low Jitter Single-Loop Clock and Data Recovery Circuit With Rotational Phase Frequency Detector.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

2013
Low Propagation Delay Load-Balanced 4 × 4 Switch Fabric IC in 0.13-µm CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2013

The direct RF power injection method up to 18 GHz for investigating IC's susceptibility.
Proceedings of the 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, 2013

2012
A Novel Low Gate-Count Pipeline Topology With Multiplexer-Flip-Flops for Serial Link.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A novel low gate-count serializer topology with Multiplexer-Flip-Flops.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Low-noise amplifiers with robust ESD protection for RF SOC.
Proceedings of the International SoC Design Conference, 2011

2009
A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18-µm CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2009

2008
A 40-Gb/s Transimpedance Amplifier in 0.18-µm CMOS Technology.
IEEE J. Solid State Circuits, 2008

A 0.18-µm CMOS Balanced Amplifier for 24-GHz Applications.
IEEE J. Solid State Circuits, 2008

2007
A Wide Locking-Range Frequency Divider for LMDS Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Miniaturization of Magnetic Resonance Microsystem Components for 3D Cell Imaging.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007


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