Yarsun Hsu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

DeAr: A framework for power-efficient and flexible embedded digital signal processor design.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015

Accelerating AdaBoost algorithm using GPU for multi-object recognition.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Message scheduling and timing analysis for flexray dynamic segment by considering slot-multiplexing.

[BibT_eX]

[DOI]

Zhan-Yao Gu

Chi-Ming Lee

Proceedings of the IEEE International Conference on Vehicular Electronics and Safety, 2015

2014

Design and Evaluation of Dynamically-Allocated Multi-queue Buffers with Multiple Packets for NoC Routers.

[BibT_eX]

[DOI]

Yung-Chou Tsai

Proceedings of the Sixth International Symposium on Parallel Architectures, 2014

A Runtime Framework for GPGPU.

[BibT_eX]

[DOI]

Shang-Chieh Lin

Proceedings of the Sixth International Symposium on Parallel Architectures, 2014

A hybrid on-chip network with a low buffer requirement.

[BibT_eX]

[DOI]

Jen-Yu Wang

Proceedings of the 20th IEEE International Conference on Parallel and Distributed Systems, 2014

Object recognition using bag of words with kernels for big data.

[BibT_eX]

[DOI]

Che-Yu Wu

Ching-Te Chiu

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2014

A Reliable and Secure GPU-Assisted File System.

[BibT_eX]

[DOI]

Shang-Chieh Lin

Yu-Cheng Liao

Proceedings of the Algorithms and Architectures for Parallel Processing, 2014

2013

Low Propagation Delay Load-Balanced 4 × 4 Switch Fabric IC in 0.13-µm CMOS Technology.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

2012

An 8 × 8 20 Gbps Reconfigurable Load Balanced TDM Switch IC for High-Speed Networking.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2012

A Novel Low Gate-Count Pipeline Topology With Multiplexer-Flip-Flops for Serial Link.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A novel low gate-count serializer topology with Multiplexer-Flip-Flops.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Achieving Global Fairness for On-Chip Network Using Group Allocation.

[BibT_eX]

[DOI]

Shan-Jung Miao

Yin Men

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Cluster-Based CAN with Enhanced Transmission Capability for Vehicle Networks.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Connected Vehicles and Expo, 2012

2011

Implementation and analysis of speculative flow control for on-chip interconnection network.

[BibT_eX]

[DOI]

Hung-Jen Sun

Proceedings of the 2nd IEEE International Conference on Networked Embedded Systems for Enterprise Applications, 2011

Group allocation: A novel fairness mechanism for on-chip network.

[BibT_eX]

[DOI]

Shan-Jung Miao

Proceedings of the 2nd IEEE International Conference on Networked Embedded Systems for Enterprise Applications, 2011

A Novel Architecture and Routing Algorithm for Dynamic Reconfigurable Network-on-Chip.

[BibT_eX]

[DOI]

Li-Wei Wu

Wei-Xiang Tang

Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2011

A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

A System Exploration Platform for Network-on-Chip.

[BibT_eX]

[DOI]

Chi-Fu Chang

Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2010

A novel MUX-FF circuit for low power and high speed serial link interfaces.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Emulation of Object-Based Storage Devices by a Virtual Machine.

[BibT_eX]

[DOI]

Yi-Chiun Fang

Chien-Kai Tseng

Proceedings of the Algorithms and Architectures for Parallel Processing, 2010

A Flexible and Cost-Effective File-Wise Reliability Scheme for Storage Systems.

[BibT_eX]

[DOI]

Tzer-Ta Tseng

Proceedings of the 12th IEEE International Conference on High Performance Computing and Communications, 2010

2009

Configurable SID-based multi-core simulators for embedded system education.

[BibT_eX]

[DOI]

Proceedings of the 2009 Workshop on Embedded Systems Education, 2009

2008

A 28Gbps 4×4 switch with low jitter SerDes using area-saving RF model in 0.13µm CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Cycle Stealing and Channel Management for On-Chip Networks.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Conference on High Performance Computing and Communications, 2008

2007

Reliable Parallel File System with Parity Cache Table Support.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2007

Design of ultra low power CML MUXs and latches with forward body bias.

[BibT_eX]

[DOI]

Hsiang-Ju Hsu

Ching-Te Chiu

Proceedings of the 2007 IEEE International SOC Conference, 2007

A Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC for High-Speed Networking Applications.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Windows-Based Parallel File System.

[BibT_eX]

[DOI]

Proceedings of the High Performance Computing and Communications, 2007

Security Enhancement and Performance Evaluation of an Object-Based Storage System.

[BibT_eX]

[DOI]

Po-Chun Liu

Proceedings of the High Performance Computing and Communications, 2007

2006

DPCT: Distributed Parity Cache Table for Redundant Parallel File System.

[BibT_eX]

[DOI]

Proceedings of the High Performance Computing and Communications, 2006

Striping Cache: A Global Cache for Striped Network File System.

[BibT_eX]

[DOI]

Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

2005

A 10 Gb/s Wide-Band Current-Mode Logic I/O Interface for High-Speed Interconnect in 0.18μm CMOS Technology.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Modularized Redundant Parallel Virtual File System.

[BibT_eX]

[DOI]

Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

2000

Memory system behavior of Java programs: methodology and analysis.

[BibT_eX]

[DOI]

Jin-Soo Kim

Proceedings of the 2000 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, 2000

1997

Parallel Systems and Parallel I/O Technology.

[BibT_eX]

[DOI]

Proceedings of the 1997 International Conference on Parallel and Distributed Systems (ICPADS '97), 1997

1996

Video on Demand Using the Vesta Parallel File System.

[BibT_eX]

[DOI]

Edgar T. Kalns

Proceedings of the Input/Output in Parallel and Distributed Computer Systems., 1996

Overview of the MPI-IO Parallel I/O Interface.

[BibT_eX]

[DOI]

Proceedings of the Input/Output in Parallel and Distributed Computer Systems., 1996

Performance Evaluation of a Massively Parallel I/O Subsystem.

[BibT_eX]

[DOI]

Proceedings of the Input/Output in Parallel and Distributed Computer Systems., 1996

1995

Efficient Stack Simulation for Set-Associative Virtual Address Cache with Real Tags.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1995

Parallel I/O subsystems in massively parallel supercomputers.

[BibT_eX]

[DOI]

Dror G. Feitelson

Peter F. Corbett

IEEE Parallel Distributed Technol. Syst. Appl., 1995

Parallel File Systems for the IBM SP Computers.

[BibT_eX]

[DOI]

IBM Syst. J., 1995

Timestamp consistency and trace-driven analysis for distributed parallel systems.

[BibT_eX]

[DOI]

Proceedings of IPPS '95, 1995

Performance Evaluation of a Parallel I/O Architecture.

[BibT_eX]

[DOI]

Proceedings of the 9th international conference on Supercomputing, 1995

1994

Performance evaluation of a massively parallel I/O subsystem.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 1994

Are We Providing the Right Education for Computer Science/Engineering Students?

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1994 International Conference on Parallel and Distributed Systems, 1994

1993

A Quantitative Evaluation of Cache Types for High-Performance Computer Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1993

Efficient Stack Simulation for Shared Memory Set-Associative Multiprocessor Caches.

[BibT_eX]

[DOI]

Proceedings of the 1993 International Conference on Parallel Processing, 1993

1992

Stack simulation for set-associative V/R-type caches.

[BibT_eX]

[DOI]

C. Eric Wu

Proceedings of the Sixteenth Annual International Computer Software and Applications Conference, 1992

1991

The Effects of Network Delays on the Performance of MIN-Based Cache Coherence Protocols.

[BibT_eX]

Proceedings of the International Conference on Parallel Processing, 1991

1990

A trace-driven analysis of the 'wrap-around' network.

[BibT_eX]

[DOI]

Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

A Design of Performance-optimized Control-based Synchronization.

[BibT_eX]

[DOI]

Sang Lyul Min

Hyoung-Joo Kim

Proceedings of the CONPAR 90, 1990

1989

A novel message switch for highly parallel systems.

[BibT_eX]

[DOI]

Shiwei Wang