Sungpack Hong

Orcid: 0009-0007-0656-2847

According to our database1, Sungpack Hong authored at least 39 papers between 2000 and 2023.

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Bibliography

2023
Retrospective: A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing.
CoRR, 2023

Distributed Asynchronous Regular Path Queries (RPQs) on Graphs.
Proceedings of the 24th International Middleware Conference Industrial Track, 2023

Better Distributed Graph Query Planning With Scouting Queries.
Proceedings of the 6th Joint Workshop on Graph Data Management Experiences & Systems (GRADES) and Network Data Analytics (NDA), 2023

Spoofax at Oracle: Domain-Specific Language Engineering for Large-Scale Graph Analytics.
Proceedings of the Eelco Visser Commemorative Symposium, 2023

2021
aDFS: An Almost Depth-First-Search Distributed Graph-Querying System.
Proceedings of the 2021 USENIX Annual Technical Conference, 2021

2020
CSR++: A Fast, Scalable, Update-Friendly Graph Data Structure.
Proceedings of the 24th International Conference on Principles of Distributed Systems, 2020

2019
Multi-level Graph Drawing Using Infomap Clustering.
Proceedings of the Graph Drawing and Network Visualization - 27th International Symposium, 2019

2018
TurboFlux: A Fast Continuous Subgraph Matching System for Streaming Graph Data.
Proceedings of the 2018 International Conference on Management of Data, 2018

2017
Modeling, analysis, and experimental comparison of streaming graph-partitioning policies.
J. Parallel Distributed Comput., 2017

A Load-Balanced Parallel and Distributed Sorting Algorithm Implemented with PGX.D.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

PGX.D/Async: A Scalable Distributed Graph Pattern Matching Engine.
Proceedings of the Fifth International Workshop on Graph Data-management Experiences & Systems, 2017

2016
Using Domain-Specific Languages For Analytic Graph Databases.
Proc. VLDB Endow., 2016

A Balanced Parallel Distributed Sorting Implemented with PGX.D.
CoRR, 2016

PGQL: a property graph query language.
Proceedings of the Fourth International Workshop on Graph Data Management Experiences and Systems, Redwood Shores, CA, USA, June 24, 2016

ASGraph: a mutable multi-versioned graph container with high analytical performance.
Proceedings of the Fourth International Workshop on Graph Data Management Experiences and Systems, Redwood Shores, CA, USA, June 24, 2016

2015
Taming Subgraph Isomorphism for RDF Query Processing.
Proc. VLDB Endow., 2015

PGX.D: a fast distributed graph processing engine.
Proceedings of the International Conference for High Performance Computing, 2015

A scalable processing-in-memory accelerator for parallel graph processing.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

Memory fast-forward: a low cost special function unit to enhance energy efficiency in GPU for big data processing.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
PGX.ISO: Parallel and Efficient In-Memory Engine for Subgraph Isomorphism.
Proceedings of the Second International Workshop on Graph Data Management Experiences and Systems, 2014

Fast In-Memory Triangle Listing for Large Real-World Graphs.
Proceedings of the 8th Workshop on Social Network Mining and Analysis, 2014

Simplifying Scalable Graph Processing with a Domain-Specific Language.
Proceedings of the 12th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2014

2013
Graph analysis: do we have to reinvent the wheel?
Proceedings of the First International Workshop on Graph Data Management Experiences and Systems, 2013

Early experiences in using a domain-specific language for large-scale graph analysis.
Proceedings of the First International Workshop on Graph Data Management Experiences and Systems, 2013

On fast parallel detection of strongly connected components (SCC) in small-world graphs.
Proceedings of the International Conference for High Performance Computing, 2013

2012
A case of system-level hardware/software co-design and co-verification of a commodity multi-processor system with custom hardware.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

Green-Marl: a DSL for easy and efficient graph analysis.
Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems, 2012

2011
Accelerating CUDA graph algorithms at maximum warp.
Proceedings of the 16th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2011

Hardware acceleration of transactional memory on commodity systems.
Proceedings of the 16th International Conference on Architectural Support for Programming Languages and Operating Systems, 2011

Efficient Parallel Graph Exploration on Multi-Core CPU and GPU.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
Eigenbench: A simple exploration tool for orthogonal TM characteristics.
Proceedings of the 2010 IEEE International Symposium on Workload Characterization, 2010

FARM: A Prototyping Environment for Tightly-Coupled, Heterogeneous Architectures.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

2008
Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution.
Proceedings of the Design, Automation and Test in Europe, 2008

2006
Runtime distribution-aware dynamic voltage scaling.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

A systematic IP and bus subsystem modeling for platform-based system design.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Creation and utilization of a virtual platform for embedded software optimization: : an industrial case study.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2003
Bus Optimization for Low Power in High-Level Synthesis.
J. Circuits Syst. Comput., 2003

2000
Decomposition of Bus-Invert Coding for Low-Power I/O.
J. Circuits Syst. Comput., 2000

Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000


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