Reetuparna Das

According to our database, Reetuparna Das authored at least 77 papers between 2007 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

nPoRe: n-polymer realigner for improved pileup-based variant calling.

Timothy Dunn, David T. Blaauw, Reetuparna Das, Satish Narayanasamy

BMC Bioinform., December, 2023

BitSET: Bit-Serial Early Termination for Computation Reduction in Convolutional Neural Networks.

Yunjie Pan, Jiecao Yu, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke

ACM Trans. Embed. Comput. Syst., October, 2023

Eidetic: An In-Memory Matrix Multiplication Accelerator for Neural Networks.

Charles Eckert, Arun Subramaniyan, Xiaowei Wang, Charles Augustine, Ravishankar Iyer, Reetuparna Das

IEEE Trans. Computers, June, 2023

GenDP: A Framework of Dynamic Programming Acceleration for Genome Sequencing Analysis.

Yufeng Gu, Arun Subramaniyan, Timothy Dunn, Alireza Khadem, Kuan-Yu Chen, Somnath Paul, Md. Vasimuddin, Sanchit Misra, David T. Blaauw, Satish Narayanasamy, Reetuparna Das

Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

Vector-Processing for Mobile Devices: Benchmark and Analysis.

Alireza Khadem, Daichi Fujiki, Nishil Talati, Scott A. Mahlke, Reetuparna Das

Proceedings of the IEEE International Symposium on Workload Characterization, 2023

2022

Hardware-friendly User-specific Machine Learning for Edge Devices.

Vidushi Goyal, Reetuparna Das, Valeria Bertacco

ACM Trans. Embed. Comput. Syst., September, 2022

Special Issue on In-Memory Computing.

Reetuparna Das

IEEE Micro, 2022

Multi-Layer In-Memory Processing.

Daichi Fujiki, Alireza Khadem, Scott A. Mahlke, Reetuparna Das

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

2021

In-/Near-Memory Computing

Daichi Fujiki, Xiaowei Wang, Arun Subramaniyan, Reetuparna Das

Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01772-8, 2021

A 2.46M Reads/s Seed-Extension Accelerator for Next-Generation Sequencing Using a String-Independent PE Array.

Zhehong Wang, Tianjun Zhang, Daichi Fujiki, Arun Subramaniyan, Xiao Wu, Makoto Yasuda, Satoru Miyoshi, Masaru Kawaminami, Reetuparna Das, Satish Narayanasamy, David T. Blaauw

IEEE J. Solid State Circuits, 2021

Cache Compression with Efficient in-SRAM Data Comparison.

Xiaowei Wang, Charles Augustine, Eriko Nurvitadhi, Ravi R. Iyer, Li Zhao, Reetuparna Das

Proceedings of the IEEE International Conference on Networking, Architecture and Storage, 2021

SquiggleFilter: An Accelerator for Portable Virus Detection.

Timothy Dunn, Harisankar Sadasivan, Jack Wadden, Kush Goliya, Kuan-Yu Chen, David T. Blaauw, Reetuparna Das, Satish Narayanasamy

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

GenomicsBench: A Benchmark Suite for Genomics.

Arun Subramaniyan, Yufeng Gu, Timothy Dunn, Somnath Paul, Md. Vasimuddin, Sanchit Misra, David T. Blaauw, Satish Narayanasamy, Reetuparna Das

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021

Accelerated Seeding for Genome Sequence Alignment with Enumerated Radix Trees.

Arun Subramaniyan, Jack Wadden, Kush Goliya, Nathan Ozog, Xiao Wu, Satish Narayanasamy, David T. Blaauw, Reetuparna Das

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs.

Xiaowei Wang, Vidushi Goyal, Jiecao Yu, Valeria Bertacco, Andrew Boutros, Eriko Nurvitadhi, Charles Augustine, Ravi R. Iyer, Reetuparna Das

Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

MyML: User-Driven Machine Learning.

Vidushi Goyal, Valeria Bertacco, Reetuparna Das

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing.

Jingcheng Wang, Xiaowei Wang, Charles Eckert, Arun Subramaniyan, Reetuparna Das, David T. Blaauw, Dennis Sylvester

IEEE J. Solid State Circuits, 2020

17.3 GCUPS Pruning-Based Pair-Hidden-Markov-Model Accelerator for Next-Generation DNA Sequencing.

Xiao Wu, Arun Subramaniyan, Zhehong Wang, Satish Narayanasamy, Reetu Das, David T. Blaauw

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

SeedEx: A Genome Sequencing Accelerator for Optimal Alignments in Subminimal Space.

Daichi Fujiki, Shunhao Wu, Nathan Ozog, Kush Goliya, David T. Blaauw, Satish Narayanasamy, Reetuparna Das

Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

Neksus: An Interconnect for Heterogeneous System-In-Package Architectures.

Vidushi Goyal, Xiaowei Wang, Valeria Bertacco, Reetuparna Das

Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2020

Seesaw: End-to-end Dynamic Sensing for IoT using Machine Learning.

Vidushi Goyal, Valeria Bertacco, Reetuparna Das

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

A 2.46M reads/s Genome Sequencing Accelerator using a 625 Processing-Element Array.

Zhehong Wang, Tianjun Zhang, Daichi Fujiki, Arun Subramaniyan, Xiao Wu, Makoto Yasuda, Satoru Miyoshi, Masaru Kawaminami, Reetuparna Das, Satish Narayanasamy, David T. Blaauw

Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

MARTINI: Memory Access Traces to Detect Attacks.

Yujun Qin, Samuel Gonzalez, Kevin Angstadt, Xiaowei Wang, Stephanie Forrest, Reetuparna Das, Kevin Leach, Westley Weimer

Proceedings of the CCSW'20, 2020

2019

TF-Net: Deploying Sub-Byte Deep Neural Networks on Microcontrollers.

Jiecao Yu, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke

ACM Trans. Embed. Comput. Syst., 2019

Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks.

Charles Eckert, Xiaowei Wang, Jingcheng Wang, Arun Subramaniyan, Dennis Sylvester, David T. Blaauw, Reetuparna Das, Ravi R. Iyer

IEEE Micro, 2019

Compute cache for data parallel acceleration.

Reetu Das

Proceedings of the 12th International Workshop on Network on Chip Architectures, 2019

A Compute SRAM with Bit-Serial Integer/Floating-Point Operations for Programmable In-Memory Vector Acceleration.

Jingcheng Wang, Xiaowei Wang, Charles Eckert, Arun Subramaniyan, Reetuparna Das, David T. Blaauw, Dennis Sylvester

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Duality cache for data parallel acceleration.

Daichi Fujiki, Scott A. Mahlke, Reetuparna Das

Proceedings of the 46th International Symposium on Computer Architecture, 2019

Bit Prudent In-Cache Acceleration of Deep Convolutional Neural Networks.

Xiaowei Wang, Jiecao Yu, Charles Augustine, Ravi R. Iyer, Reetuparna Das

Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

2018

ASPEN: A Scalable In-SRAM Architecture for Pushdown Automata.

Kevin Angstadt, Arun Subramaniyan, Elaheh Sadredini, Reza Rahimi, Kevin Skadron, Westley Weimer, Reetuparna Das

Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

GenAx: A Genome Sequencing Accelerator.

Daichi Fujiki, Arun Subramaniyan, Tianjun Zhang, Yu Zeng, Reetuparna Das, David T. Blaauw, Satish Narayanasamy

Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

In-Memory Data Parallel Processor.

Daichi Fujiki, Scott A. Mahlke, Reetuparna Das

Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017

Blurring the Lines between Memory and Computation.

Reetuparna Das

IEEE Micro, 2017

Mirage cores: the illusion of many out-of-order cores using in-order hardware.

Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Cache automaton.

Arun Subramaniyan, Jingcheng Wang, Ezhil R. M. Balasubramanian, David T. Blaauw, Dennis Sylvester, Reetuparna Das

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Scalpel: Customizing DNN Pruning to the Underlying Hardware Parallelism.

Jiecao Yu, Andrew Lukefahr, David J. Palframan, Ganesh S. Dasika, Reetuparna Das, Scott A. Mahlke

Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

Parallel Automata Processor.

Arun Subramaniyan, Reetuparna Das

Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

Cold Boot Attacks are Still Hot: Security Analysis of Memory Scramblers in Modern Processors.

Salessawi Ferede Yitbarek, Misiker Tadesse Aga, Reetuparna Das, Todd M. Austin

Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Compute Caches.

Shaizeen Aga, Supreet Jeloka, Arun Subramaniyan, Satish Narayanasamy, David T. Blaauw, Reetuparna Das

Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

In-memory Data Flow Processor.

Daichi Fujiki, Scott A. Mahlke, Reetuparna Das

Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

Cache Automaton: Repurposing Caches for Automata Processing.

Arun Subramaniyan, Jingcheng Wang, Ezhil R. M. Balasubramanian, David T. Blaauw, Dennis Sylvester, Reetuparna Das

Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016

Exploring Fine-Grained Heterogeneity with Composite Cores.

Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Faissal M. Sleiman, Ronald G. Dreslinski, Thomas F. Wenisch, Scott A. Mahlke

IEEE Trans. Computers, 2016

A case for hierarchical rings with deflection routing: An energy-efficient on-chip communication substrate.

Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Kai-Wei Chang, Greg Nazario, Reetuparna Das, Gabriel H. Loh, Onur Mutlu

Parallel Comput., 2016

Achieving both High Energy Efficiency and High Performance in On-Chip Communication using Hierarchical Rings with Deflection Routing.

Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Kai-Wei Chang, Greg Nazario, Reetuparna Das, Gabriel H. Loh, Onur Mutlu

CoRR, 2016

Exploring specialized near-memory processing for data intensive operations.

Salessawi Ferede Yitbarek, Tao Yang, Reetuparna Das, Todd M. Austin

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

ANVIL: Software-Based Protection Against Next-Generation Rowhammer Attacks.

Zelalem Birhanu Aweke, Salessawi Ferede Yitbarek, Rui Qiao, Reetuparna Das, Matthew Hicks, Yossi Oren, Todd M. Austin

Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems, 2016

2015

DynaMOS: dynamic schedule migration for heterogeneous cores.

Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke

Proceedings of the 48th International Symposium on Microarchitecture, 2015

Locking down insecure indirection with hardware-based control-data isolation.

William Arthur, Sahil Madeka, Reetuparna Das, Todd M. Austin

Proceedings of the 48th International Symposium on Microarchitecture, 2015

Getting in control of your control flow with control-data isolation.

William Arthur, Ben Mehne, Reetuparna Das, Todd M. Austin

Proceedings of the 13th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2015

2014

Design and Evaluation of Hierarchical Rings with Deflection Routing.

Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Kai-Wei Chang, Greg Nazario, Reetuparna Das, Gabriel H. Loh, Onur Mutlu

Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

Hi-Rise: A High-Radix Switch for 3D Integration with Single-Cycle Arbitration.

Supreet Jeloka, Reetuparna Das, Ronald G. Dreslinski, Trevor N. Mudge, David T. Blaauw

Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

VIX: Virtual Input Crossbar for Efficient Switch Allocation.

Supriya Rao, Supreet Jeloka, Reetuparna Das, David T. Blaauw, Ronald G. Dreslinski, Trevor N. Mudge

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Power-Aware NoCs through Routing and Topology Reconfiguration.

Ritesh Parikh, Reetuparna Das, Valeria Bertacco

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Quality-of-Service for a High-Radix Switch.

Nilmini Abeyratne, Supreet Jeloka, Yiping Kang, David T. Blaauw, Ronald G. Dreslinski, Reetuparna Das, Trevor N. Mudge

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Heterogeneous microarchitectures trump voltage scaling for low-power cores.

Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Ronald G. Dreslinski, Thomas F. Wenisch, Scott A. Mahlke

Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

2013

Trace based phase prediction for tightly-coupled heterogeneous cores.

Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

Catnap: energy proportional multiple network-on-chip.

Reetuparna Das, Satish Narayanasamy, Sudhir Satpathy, Ronald G. Dreslinski

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

Application-to-core mapping policies to reduce memory system interference in multi-core systems.

Reetuparna Das, Rachata Ausavarungnirun, Onur Mutlu, Akhilesh Kumar, Mani Azimi

Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

Scaling towards kilo-core processors with asymmetric high-radix topologies.

Nilmini Abeyratne, Reetuparna Das, Qingkun Li, Korey Sewell, Bharan Giridhar, Ronald G. Dreslinski, David T. Blaauw, Trevor N. Mudge

Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2012

Swizzle-Switch Networks for Many-Core Systems.

Korey Sewell, Ronald G. Dreslinski, Thomas Manville, Sudhir Satpathy, Nathaniel Ross Pinckney, Geoffrey Blake, Michael Cieslak, Reetuparna Das, Thomas F. Wenisch, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge

IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

Composite Cores: Pushing Heterogeneity Into a Core.

Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Faissal M. Sleiman, Ronald G. Dreslinski, Thomas F. Wenisch, Scott A. Mahlke

Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Swizzle Switch: A self-arbitrating high-radix crossbar for NoC systems.

Ronald G. Dreslinski, Korey Sewell, Thomas Manville, Sudhir Satpathy, Nathaniel Ross Pinckney, Geoffrey Blake, Michael Cieslak, Reetuparna Das, Thomas F. Wenisch, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge

Proceedings of the 2012 IEEE Hot Chips 24 Symposium (HCS), 2012

High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service.

Sudhir Satpathy, Reetuparna Das, Ronald G. Dreslinski, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

XPoint cache: scaling existing bus-based coherence protocols for 2D and 3D many-core systems.

Ronald G. Dreslinski, Thomas Manville, Korey Sewell, Reetuparna Das, Nathaniel Ross Pinckney, Sudhir Satpathy, David T. Blaauw, Dennis Sylvester, Trevor N. Mudge

Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

Application-to-core mapping policies to reduce memory interference in multi-core systems.

Reetuparna Das, Rachata Ausavarungnirun, Onur Mutlu, Akhilesh Kumar, Mani Azimi

Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011

Aérgia: A Network-on-Chip Exploiting Packet Latency Slack.

Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das

IEEE Micro, 2011

RAFT: A router architecture with frequency tuning for on-chip networks.

Asit K. Mishra, Aditya Yanamandra, Reetuparna Das, Soumya Eachempati, Ravi R. Iyer, Narayanan Vijaykrishnan, Chita R. Das

J. Parallel Distributed Comput., 2011

2010

Aérgia: exploiting packet latency slack in on-chip networks.

Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das

Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

Cost-driven 3D integration with interconnect layers.

Xiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna Das, Yuan Xie, Chita R. Das, Jian Li

Proceedings of the 47th Design Automation Conference, 2010

2009

A case for integrated processor-cache partitioning in chip multiprocessors.

Shekhar Srikantaiah, Reetuparna Das, Asit K. Mishra, Chita R. Das, Mahmut T. Kandemir

Proceedings of the ACM/IEEE Conference on High Performance Computing, 2009

A case for dynamic frequency tuning in on-chip networks.

Asit K. Mishra, Reetuparna Das, Soumya Eachempati, Ravishankar R. Iyer, Narayanan Vijaykrishnan, Chita R. Das

Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Application-aware prioritization mechanisms for on-chip networks.

Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das

Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs.

Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das

Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

2008

MIRA: A Multi-layered On-Chip Interconnect Router Architecture.

Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das

Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

Performance and power optimization through data compression in Network-on-Chip architectures.

Reetuparna Das, Asit K. Mishra, Chrysostomos Nicopoulos, Dongkook Park, Vijaykrishnan Narayanan, Ravishankar R. Iyer, Mazin S. Yousif, Chita R. Das

Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008

2007

A novel dimensionally-decomposed router for on-chip communication in 3D architectures.

Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das

Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects.

Dongkook Park, Reetuparna Das, Chrysostomos Nicopoulos, Jongman Kim, Narayanan Vijaykrishnan, Ravishankar R. Iyer, Chita R. Das

Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects, 2007