Mustafa Karaköy

Orcid: 0000-0001-7499-0834

According to our database1, Mustafa Karaköy authored at least 50 papers between 2002 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
Data Recomputation for Multithreaded Applications.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Architecture-Aware Currying.
Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023

2022
Memory Space Recycling.
Proc. ACM Meas. Anal. Comput. Syst., 2022

Fine-Granular Computation and Data Layout Reorganization for Improving Locality.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

2021
Mix and Match: Reorganizing Tasks for Enhancing Data Locality.
Proc. ACM Meas. Anal. Comput. Syst., 2021

Compiler support for near data computing.
Proceedings of the PPoPP '21: 26th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2021

Distance-in-time versus distance-in-space.
Proceedings of the PLDI '21: 42nd ACM SIGPLAN International Conference on Programming Language Design and Implementation, 2021

2020
Collective Affinity Aware Computation Mapping.
Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020

2019
Architecture-Aware Approximate Computing.
Proc. ACM Meas. Anal. Comput. Syst., 2019

Co-optimizing memory-level parallelism and cache-level parallelism.
Proceedings of the 40th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2019

2018
Computing with Near Data.
Proc. ACM Meas. Anal. Comput. Syst., 2018

2017
Data movement aware computation partitioning.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

2015
Memory Row Reuse Distance and its Role in Optimizing Application Performance.
Proceedings of the 2015 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, 2015

2011
Multilayer Cache Partitioning for Multiprogram Workloads.
Proceedings of the Euro-Par 2011 Parallel Processing - 17th International Conference, 2011

Compiler Directed Data Locality Optimization for Multicore Architectures.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
Cashing in on hints for better prefetching and caching in PVFS and MPI-IO.
Proceedings of the 19th ACM International Symposium on High Performance Distributed Computing, 2010

Computation mapping for multi-level storage cache hierarchies.
Proceedings of the 19th ACM International Symposium on High Performance Distributed Computing, 2010

2009
Reducing memory requirements of resource-constrained applications.
ACM Trans. Embed. Comput. Syst., 2009

A compiler-directed data prefetching scheme for chip multiprocessors.
Proceedings of the 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2009

2008
Prefetch throttling and data pinning for improving performance of shared caches.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2008

Improving I/O performance through compiler-directed code restructuring and adaptive prefetching.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Integrated code and data placement in two-dimensional mesh based chip multiprocessors.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Improving I/O Performance of Applications through Compiler-Directed Code Restructuring.
Proceedings of the 6th USENIX Conference on File and Storage Technologies, 2008

Profiler and compiler assisted adaptive I/O prefetching for shared storage caches.
Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008

2007
A Constraint Network Based Approach to Memory Layout Optimization
CoRR, 2007

A Process Scheduler-Based Approach to NoC Power Management.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Improving disk reuse for reducing power consumption.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Compiler-Directed Variable Latency Aware SPM Management to CopeWith Timing Problems.
Proceedings of the Fifth International Symposium on Code Generation and Optimization (CGO 2007), 2007

2006
Compiler Support for Voltage Islands.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

An Integer Linear Programming Based Approach to Simultaneous Memory Space Partitioning and Data Allocation for Chip Multiprocessors.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Cache miss clustering for banked memory systems.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Selective code/data migration for reducing communication energy in embedded MpSoC architectures.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Dynamic scratch-pad memory management for irregular array access patterns.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Optimizing Array-Intensive Applications for On-Chip Multiprocessors.
IEEE Trans. Parallel Distributed Syst., 2005

Reducing data cache leakage energy using a compiler-based approach.
ACM Trans. Embed. Comput. Syst., 2005

Workload Clustering for Increasing Energy Savings on Embedded MPSoCs.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Memory Space Conscious Loop Iteration Duplication for Reliable Execution.
Proceedings of the Static Analysis, 12th International Symposium, 2005

Exploiting last idle periods of links for network power management.
Proceedings of the EMSOFT 2005, 2005

A Data-Centric Approach to Checksum Reuse for Array-Intensive Applications.
Proceedings of the 2005 International Conference on Dependable Systems and Networks (DSN 2005), 28 June, 2005

A Constraint Network Based Approach to Memory Layout Optimization.
Proceedings of the 2005 Design, 2005

Customized on-chip memories for embedded chip multiprocessors.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Dynamic on-chip memory management for chip multiprocessors.
Proceedings of the 2004 International Conference on Compilers, 2004

2003
Loop Transformations for Reducing Data Space Requirements of Resource-Constrained Applications.
Proceedings of the Static Analysis, 10th International Symposium, 2003

A Rule-Based Scheme for Filtering Examples from Majority Class in an Imbalanced Training Set.
Proceedings of the Machine Learning and Data Mining in Pattern Recognition, 2003

A compiler approach for reducing data cache energy.
Proceedings of the 17th Annual International Conference on Supercomputing, 2003

An Energy-Oriented Evaluation of Communication Optimizations for Microcensor Networks.
Proceedings of the Euro-Par 2003. Parallel Processing, 2003

Runtime Code Parallelization for On-Chip Multiprocessors.
Proceedings of the 2003 Design, 2003

Interprocedural optimizations for improving data cache performance of array-intensive embedded applications.
Proceedings of the 40th Design Automation Conference, 2003

Dynamic Parallelization of Array Based On-Chip Multiprocessor Applications.
Proceedings of the Embedded Software for SoC, 2003

2002
An energy saving strategy based on adaptive loop parallelization.
Proceedings of the 39th Design Automation Conference, 2002


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