Shin-ya Abe

According to our database, Shin-ya Abe authored at least 10 papers between 2012 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating.

Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa

Inf. Media Technol., 2015

A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs.

Koichi Fujiwara, Kazushi Kawamura, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design.

Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

2014

A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs.

Koichi Fujiwara, Shin-ya Abe, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling.

Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa

Inf. Media Technol., 2013

Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages.

Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages.

Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

2012

Energy-efficient High-level Synthesis for HDR Architectures.

Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa

Inf. Media Technol., 2012

MH⁴ : multiple-supply-voltages aware high-level synthesis for high-integrated and high-frequency circuits for HDR architectures.

Shin-ya Abe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa

IEICE Electron. Express, 2012

An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures.

Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012