Kimiyoshi Usami

According to our database1, Kimiyoshi Usami authored at least 67 papers between 1990 and 2018.

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Bibliography

2018
A Coarse Grained-Reconfigurable Accelerator with energy efficient MTJ-based Non-volatile Flip-flops.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application.
Proceedings of the IEEE 7th Non-Volatile Memory Systems and Applications Symposium, 2018

2017
Power Optimization Methodology for Ultralow Power Microcontroller With Silicon on Thin BOX MOSFET.
IEEE Trans. VLSI Syst., 2017

Energy-Efficient Standard Cell Memory with Optimized Body-Bias Separation in Silicon-on-Thin-BOX (SOTB).
IEICE Transactions, 2017

Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI.
Proceedings of the VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things, 2017

Level-shifter-less approach for multi-VDD design to use body bias control in FD-SOI.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor.
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017

Digital embedded memory scheme using voltage scaling and body bias separation for low-power system.
Proceedings of the International SoC Design Conference, 2017

Building block multi-chip systems using inductive coupling through chip interface.
Proceedings of the International SoC Design Conference, 2017

2016
An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications.
IEICE Transactions, 2016

Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-Power Network-on-Chips Systems.
IEICE Transactions, 2016

2015
A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units.
IEICE Transactions, 2015

A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode.
IEICE Transactions, 2015

An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design.
IEICE Transactions, 2015

An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

A leakage current monitor circuit using silicon on thin BOX MOSFET for dynamic back gate bias control.
Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015

2014
A Thermal Management System for Building Block Computing Systems.
Proceedings of the IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, 2014

Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating.
Proceedings of the 2014 International Symposium on System-on-Chip, 2014

A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode.
Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014

Design and evaluation of fine-grained power-gating for embedded microprocessors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014

Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface.
IEEE Micro, 2013

Foreword.
IEICE Transactions, 2013

Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design.
IEICE Transactions, 2013

Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages.
IEICE Transactions, 2013

An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface.
Proceedings of the 2013 IEEE Symposium on Low-Power and High-Speed Chips, 2013

2012
Geyser.
Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012

Fine-Grained Power Control Using A Multi-Voltage Variable Pipeline Router.
Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012

Efficient leakage power saving by sleep depth controlling for Multi-mode Power Gating.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Stepwise sleep depth control for run-time leakage power saving.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Trade-off analysis of fine-grained power gating methods for functional units in a CPU.
Proceedings of the 2012 IEEE Symposium on Low-Power and High-Speed Chips, 2012

A multi-Vdd dynamic variable-pipeline on-chip router for CMPs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips.
IEEE Micro, 2011

Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units.
IPSJ Trans. System LSI Design Methodology, 2011

Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model.
IEICE Transactions, 2011

On-chip detection methodology for break-even time of power gated function units.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Cool Mega-Array: A highly energy efficient reconfigurable accelerator.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator.
Proceedings of the 2011 IEEE Symposium on Low-Power and High-Speed Chips, 2011

Geyser-2: The second prototype CPU with fine-grained run-time power gating.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Dynamic VDD Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010
Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs.
Proceedings of the NOCS 2010, 2010

Adaptive power gating for function units in a microprocessor.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Cache Controller Design on Ultra Low Leakage Embedded Processors.
Proceedings of the Architecture of Computing Systems, 2009

2008
A fine-grain dynamic sleep control scheme in MIPS R3000.
Proceedings of the 26th International Conference on Computer Design, 2008

Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Power Gating for Ultra-low Leakage: Physics, Design, and Analysis.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Overview on Low Power SoC Design Technology.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Delay Modeling and Critical-Path Delay Calculation for MTCMOS Circuits.
IEICE Transactions, 2006

A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Delay modeling and static timing analysis for MTCMOS circuits.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2002
Code Coverage-Based Power Estimation Techniques for Microprocessors.
Journal of Circuits, Systems, and Computers, 2002

Automated selective multi-threshold design for ultra-low standby applications.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

2000
Function-level power estimation methodology for microprocessors.
Proceedings of the 37th Conference on Design Automation, 2000

Low-power design methodology and applications utilizing dual supply voltages.
Proceedings of ASP-DAC 2000, 2000

1998
Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques.
Proceedings of the 35th Conference on Design Automation, 1998

A Clock-Gating Method for Low-Power LSI Design.
Proceedings of the ASP-DAC '98, 1998

1997
A low-power design method using multiple supply voltages.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

1995
Clustered voltage scaling technique for low-power design.
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

1990
Datapath Generator Based on Gate-Level Symbolic Layout.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990


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