Shounak Dhar

According to our database, Shounak Dhar authored at least 12 papers between 2016 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.

Yibo Lin, Zixuan Jiang, Jiaqi Gu, Wuxi Li, Shounak Dhar, Haoxing Ren, Brucek Khailany, David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

2019

FPGA-Accelerated Spreading for Global Placement.

Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan

Proceedings of the 2019 IEEE High Performance Extreme Computing Conference, 2019

FPGA Accelerated FPGA Placement.

Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.

Yibo Lin, Shounak Dhar, Wuxi Li, Haoxing Ren, Brucek Khailany, David Z. Pan

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A shape-driven spreading algorithm using linear programming for global placement.

Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine.

Wuxi Li, Yibo Lin, Meng Li, Shounak Dhar, David Z. Pan

ACM Trans. Design Autom. Electr. Syst., 2018

UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing.

Wuxi Li, Shounak Dhar, David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

GDP: GPU accelerated Detailed Placement.

Shounak Dhar, David Z. Pan

Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018

Logic synthesis for energy-efficient photonic integrated circuits.

Zheng Zhao, Zheng Wang, Zhoufeng Ying, Shounak Dhar, Ray T. Chen, David Z. Pan

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

An Effective Timing-Driven Detailed Placement Algorithm for FPGAs.

Shounak Dhar, Mahesh A. Iyer, Saurabh N. Adya, Love Singhal, Nikolay Rubanov, David Z. Pan

Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

Optical computing on silicon-on-insulator-based photonic integrated circuits.

Zheng Zhao, Zheng Wang, Zhoufeng Ying, Shounak Dhar, Ray T. Chen, David Z. Pan

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

Detailed placement for modern FPGAs using 2D dynamic programming.

Shounak Dhar, Saurabh N. Adya, Love Singhal, Mahesh A. Iyer, David Z. Pan

Proceedings of the 35th International Conference on Computer-Aided Design, 2016