Shounak Dhar

According to our database1, Shounak Dhar authored at least 11 papers between 2016 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
FPGA-Accelerated Spreading for Global Placement.
Proceedings of the 2019 IEEE High Performance Extreme Computing Conference, 2019

FPGA Accelerated FPGA Placement.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A shape-driven spreading algorithm using linear programming for global placement.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine.
ACM Trans. Design Autom. Electr. Syst., 2018

UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

GDP: GPU accelerated Detailed Placement.
Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018

Logic synthesis for energy-efficient photonic integrated circuits.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
An Effective Timing-Driven Detailed Placement Algorithm for FPGAs.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

Optical computing on silicon-on-insulator-based photonic integrated circuits.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
Detailed placement for modern FPGAs using 2D dynamic programming.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016


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