Shouzhen Gu

Orcid: 0000-0003-2560-4209

According to our database1, Shouzhen Gu authored at least 34 papers between 2013 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
A Differentially Private Federated Learning Model Against Poisoning Attacks in Edge Computing.
IEEE Trans. Dependable Secur. Comput., 2023

Rapid recovery of program execution under power failures for embedded systems with NVM.
Microprocess. Microsystems, 2023

Single-shot decoding of good quantum LDPC codes.
CoRR, 2023

An Efficient Decoder for a Linear Distance Quantum LDPC Code.
Proceedings of the 55th Annual ACM Symposium on Theory of Computing, 2023

2022
Transient computing for energy harvesting systems: A survey.
J. Syst. Archit., 2022

Fairness Scheduling for Tasks with Different Real-time Level on Heterogeneous Systems.
Proceedings of the 28th IEEE International Conference on Parallel and Distributed Systems, 2022

Work-in-Progress: Cooperative MLP-Mixer Networks Inference On Heterogeneous Edge Devices through Partition and Fusion.
Proceedings of the International Conference on Compilers, 2022

2021
Fast-forwarding quantum evolution.
Quantum, 2021

Optimizing the data placement and scheduling on multi-port DWM in multi-core embedded system.
J. Syst. Archit., 2021

Performance optimization for parallel systems with shared DWM via retiming, loop scheduling, and data placement.
J. Syst. Archit., 2021

Relaxed Placement: Minimizing Shift Operations for Racetrack Memory in Hybrid SPM.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020
Hardware/Software Co-Exploration of Neural Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Towards the design of efficient hash-based indexing scheme for growing databases on non-volatile memory.
Future Gener. Comput. Syst., 2020

Architectural Exploration on Racetrack Memories.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

Optimizing Data Placement for Hybrid SPM with SRAM and Racetrack Memory.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

An Empirical Study of Hybrid SSD with Optane and QLC Flash.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2019
Hardware/Software Co-Exploration of Neural Architectures.
CoRR, 2019

A Wear-Leveling-Aware Fine-Grained Allocator for Non-Volatile Memory.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Write-Aware Data Allocation on Heterogeneous Memory Architecture with Minimum Cost.
Proceedings of the 24th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2018

2017
An Efficient Racetrack Memory-Based Processing-in-Memory Architecture for Convolutional Neural Networks.
Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017

Efficient Task Assignment and Scheduling on MPSOC with STT-RAM Based Hybrid SPMs Considering Data Allocation.
Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017

2016
Data Allocation with Minimum Cost under Guaranteed Probability for Multiple Types of Memories.
J. Signal Process. Syst., 2016

Wear-Leveling Aware Page Management for Non-Volatile Main Memory on Embedded Systems.
IEEE Trans. Multi Scale Comput. Syst., 2016

A Time, Energy, and Area Efficient Domain Wall Memory-Based SPM for Embedded Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

2015
Reliability-Guaranteed Task Assignment and Scheduling for Heterogeneous Multiprocessors Considering Timing Constraint.
J. Signal Process. Syst., 2015

Optimizing Task and Data Assignment on Multi-Core Systems with Multi-Port SPMs.
IEEE Trans. Parallel Distributed Syst., 2015

Area and performance co-optimization for domain wall memory in application-specific embedded systems.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Minimizing System Cost with Efficient Task Assignment on Heterogeneous Multicore Processors Considering Time Constraint.
IEEE Trans. Parallel Distributed Syst., 2014

Scheduling to Optimize Cache Utilization for Non-Volatile Main Memories.
IEEE Trans. Computers, 2014

A space allocation and reuse strategy for PCM-based embedded systems.
J. Syst. Archit., 2014

Minimum-cost data allocation with guaranteed probability on multiple types of memory.
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014

2013
Optimizing task assignment for heterogeneous multiprocessor system with guaranteed reliability and timing constraint.
Proceedings of the 2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications, 2013

A space-based wear leveling for PCM-based embedded systems.
Proceedings of the 2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications, 2013

Efficient task assignment and scheduling for MPSoC DSPS with VS-SPM considering concurrent accesses through data allocation.
Proceedings of the IEEE International Conference on Acoustics, 2013


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