Shuang Liang

Orcid: 0000-0003-0881-5549

Affiliations:
  • Tsinghua University, Institute of Microelectronics, Beijing, China


According to our database1, Shuang Liang authored at least 12 papers between 2011 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
DeepStack: Scalable and Accurate Design Space Exploration for Distributed 3D-Stacked AI Accelerators.
CoRR, April, 2026

Advancing Full-Stack Acceleration for SchröDinger-Style Quantum Simulation.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2026

FastTTS: Accelerating Test-Time Scaling for Edge LLM Reasoning.
Proceedings of the 31st ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2026

Hardware-Efficient Union-Find Decoder Towards Scalable Topological Quantum Codes.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025
Democratizing Agentic AI with Fast Test-Time Scaling on the Edge.
CoRR, September, 2025

Versatile Cross-platform Compilation Toolchain for Schrödinger-style Quantum Circuit Simulation.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2024
PCQ: Parallel Compact Quantum Circuit Simulation.
Proceedings of the 32nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2024

2018
FP-BNN: Binarized neural network on FPGA.
Neurocomputing, 2018

2016
A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration.
IEEE Comput. Archit. Lett., 2016

Relation-oriented resource allocation for multi-accelerator systems.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015
The Implementation of Texture-Based Video Up-Scaling on Coarse-Grained Reconfigurable Architecture.
IEICE Trans. Inf. Syst., 2015

2011
Performance evaluation modeling for reconfigurable processor.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011


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